A3957SLB Allegro, A3957SLB Datasheet - Page 9

• Manufacturer Part Number: A3957SLB
• Description: Full Bridge PWM Motor Driver 5V 24-Pin SOIC W
• Manufacturer: Allegro
• Type: Full Bridge PWM Motor Driverr

Specifications of A3957SLB

• Package: 24SOIC W
• Operating Supply Voltage: 5 V
• Maximum Operating Current: 4 mA
• Operating Temperature: -20 to 85 °C

drivers are needed to drive the windings of a bipolar stepper
motor. Internal pulse-width modulated (PWM) control circuitry
regulates each motor winding’s current. The peak motor
current is set by the value of an external current-sense resistor
(R
converter (DAC) data inputs (D
sinusoidal current profiles necessary for microstepping, the
A3957S— has three distinct current-decay modes: slow decay,
fast decay, and mixed decay.
PHASE Input. The PHASE input controls the direction of
current flow in the load (table 1). An internally generated dead
time of approximately 1.5 s prevents crossover currents that
could occur when switching the PHASE input.
DAC Data Inputs (D
to digitally control the output current. The output of the DAC is
used to set the trip point of the current-sense comparator. Table
3 shows DAC output voltages for each input condition. When
D
transistors are turned off.
Internal PWM Current Control. Each motor driver IC
contains an internal fixed off-time PWM current-control circuit
that limits the load current to a desired value (I
diagonal pair of source and sink transistors are enabled and
current flows through the motor winding and R
1
3957
FULL-BRIDGE PWM
MICROSTEPPING
MOTOR DRIVER
S
, D
), a reference voltage (V
Two A3957S— full-bridge PWM microstepping motor
To improve motor performance, especially when using
2
, and D
Figure 1 — Load-Current Paths
3
are all logic low, all of the power output
Functional Description
R S
0
, D
V
BB
1
, D
REF
2
, D
), and the digital-to-analog
0
, D
3
). A non-linear DAC is used
1
, D
DRIVE CURRENT
RECIRCULATION
(SLOW-DECAY MODE)
RECIRCULATION
(FAST-DECAY MODE)
2
, and D
TRIP
S
Dwg. EP-006-15
3
).
(figure 1).
). Initially, a
When the voltage across the sense resistor equals the DAC
output voltage, the current-sense comparator resets the PWM
latch, which turns off the source drivers (slow-decay mode) or
the sink and source drivers (fast- or mixed-decay mode).
value of current limiting is set by the selection of R
with a transconductance function approximated by:
where I
current of the sink transistor (typically 30 mA). The actual peak
load current (I
internal logic and switching delays. The driver(s) remain off
for a time period determined by a user-selected external
resistor-capacitor combination (R
off time, the driver(s) are re-enabled, allowing the load current
to increase to I
mately 16 mV. With R
is effectively cancelled (V
levels of output current. The internal 4-bit digital-to-analog
converter reduces the reference input to the current-sense
comparator in precise steps (the step reference current ratio or
SRCR) to provide half-step, quarter-step, eighth-step, or
“microstepping” load-current levels.
Slow Current-Decay Mode. When V
in slow current-decay mode (the source drivers are disabled
when the load current reaches I
the load inductance causes the current to recirculate through the
motor winding, sink driver, ground clamp diode, and sense
resistor (see figure 1). Slow-decay mode produces low ripple
current for a given fixed off time (see figure 2). Low ripple
current is desirable because the average current in the motor
winding is more nearly equal to the desired reference value,
resulting in increased motor performance in microstepping
applications.
lowest PWM frequency, which reduces heating in the motor and
driver IC due to a corresponding decrease in hysteretic core
losses and switching losses respectively. Slow decay also has
the advantage that the PWM load current regulation can follow
a more rapidly increasing reference before the PWM frequency
drops into the audible range. For these reasons slow-decay
mode is typically used as long as good current regulation can be
maintained.
With the DATA input lines tied to V
The current-sense comparator has a fixed offset of approxi-
The DAC data input lines are used to provide up to eight
For a given level of ripple current, slow decay affords the
SO
is the sense-current offset due to the base-drive
PEAK
TRIP
I
TRIP
) will be slightly higher than I
again, maintaining an average load current.
I
TRIP
S
V
= 0.5 , the sense-current offset (I
REF
IO(S)
SRCR x V
/3R
TRIP
S
I
T
SO
= I
C
). During the fixed off time,
T
• R
REF
OUT
). At the end of the fixed
PFD
S
/3R
).
CC
+ I
, the maximum
S
SO
3.5 V, the device is
.
TRIP
S
and V
due to
REF
SO
)