XC2VP70-7FF1517C Xilinx Inc, XC2VP70-7FF1517C Datasheet - Page 57

• Manufacturer Part Number: XC2VP70-7FF1517C
• Description: FPGA Virtex-II Pro Family 74448 Cells 1350MHz 0.13um/90nm (CMOS) Technology 1.5V 1517-Pin FCBGA
• Manufacturer: Xilinx Inc

Specifications of XC2VP70-7FF1517C

• Package: 1517FCBGA
• Family Name: Virtex-II Pro
• Device Logic Units: 74448
• Number Of Registers: 66176
• Maximum Internal Frequency: 1350 MHz
• Typical Operating Supply Voltage: 1.5 V
• Maximum Number Of User I/os: 964
• Ram Bits: 6045696
• Re-programmability Support: Yes

Each block SelectRAM+ cell is a fully synchronous memory,
as illustrated in
inputs and outputs and are independently clocked.
Port Aspect Ratios
Table 23
18 Kb block SelectRAM+ resource. Virtex-II Pro block
SelectRAM+ also includes dedicated routing resources to
provide an efficient interface with CLBs, block SelectRAM+,
and multipliers.
Table 23: 18 Kb Block SelectRAM+ Port Aspect Ratio
Read/Write Operations
The Virtex-II Pro block SelectRAM+ read operation is fully
synchronous. An address is presented, and the read opera-
tion is enabled by control signal ENA or ENB. Then,
depending on clock polarity, a rising or falling clock edge
causes the stored data to be loaded into output registers.
The write operation is also fully synchronous. Data and
address are presented, and the write operation is enabled
by control signals WEA and WEB in addition to ENA or
ENB. Then, again depending on the clock input mode, a ris-
DS083 (v4.7) November 5, 2007
Product Specification
Figure 48: 18 Kb Block SelectRAM+ in Dual-Port Mode
Width
18
36
1
2
4
9
shows the depth and the width aspect ratios for the
16,384
Depth
8,192
4,096
2,048
1,024
512
R
Figure
DIB
DIPA
ADDRA
WEA
ENA
SSRA
DIPB
ADDRB
WEB
ENB
SSRB
DIA
Address Bus
CLKA
CLKB
ADDR[13:0]
ADDR[12:0]
ADDR[11:0]
ADDR[10:0]
18-Kbit Block SelectRAM
ADDR[9:0]
ADDR[8:0]
48. The two ports have independent
DATA[15:0]
DATA[31:0]
Data Bus
DATA[1:0]
DATA[3:0]
DATA[7:0]
DATA[0]
DOPA
DOPB
DOA
DOB
DS031_11_102000
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
Parity Bus
Parity[1:0]
Parity[3:0]
Parity[0]
N/A
N/A
N/A
www.xilinx.com
ing or falling clock edge causes the data to be loaded into
the memory cell addressed.
A write operation performs a simultaneous read operation.
Three different options are available, selected by configura-
tion:
1. WRITE_FIRST
2. READ_FIRST
The READ_FIRST option is a read-before-write mode.
The same clock edge that writes data input (DI) into the
memory also transfers the prior content of the memory cell
addressed into the data output registers DO, as shown in
Figure
RAM Contents
RAM Contents
The WRITE_FIRST option is a transparent mode. The
same clock edge that writes the data input (DI) into the
memory also transfers DI into the output registers DO,
as shown in
Data_out
Data_out
Address
Address
Data_in
Data_in
Data_in
Data_in
50.
CLK
CLK
WE
WE
Figure 49: WRITE_FIRST Mode
Figure 50: READ_FIRST Mode
Figure
DI
DI
New
New
Old
Old
aa
aa
Internal
Internal
Memory
Memory
49.
DO
DO
Prior stored data
Data_out = Data_in
New
New
New
Old
DS083-2_14_050901
DS083-2_13_050901
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