XC2S600E-6FG676C Xilinx Inc, XC2S600E-6FG676C Datasheet - Page 43

• Manufacturer Part Number: XC2S600E-6FG676C
• Description: FPGA Spartan-IIE Family 600K Gates 15552 Cells 357MHz 0.15um Technology 1.8V 676-Pin FBGA
• Manufacturer: Xilinx Inc

Specifications of XC2S600E-6FG676C

• Package: 676FBGA
• Family Name: Spartan-IIE
• Device Logic Cells: 15552
• Device Logic Units: 3456
• Device System Gates: 600000
• Maximum Internal Frequency: 357 MHz
• Typical Operating Supply Voltage: 1.8 V
• Maximum Number Of User I/os: 514
• Ram Bits: 294912
• Re-programmability Support: Yes

DLL Timing Parameters
Because of the difficulty in directly measuring many internal
timing parameters, those parameters are derived from
benchmark timing patterns. The following guidelines reflect
DLL Clock Tolerance, Jitter, and Phase Information
All DLL output jitter and phase specifications were deter-
mined through statistical measurement at the package pins
using a clock mirror configuration and matched drivers.
DS077-3 (v2.3) June 18, 2008
Product Specification
Notes:
1.
2.
3.
4.
5.
6.
T
Symbol
T
T
T
T
T
T
T
PHOOM
OJITCC
PHIOM
IJITCC
IPTOL
PHOO
LOCK
Commercial operating conditions. Add 30% for Industrial operating conditions.
Output Jitter is cycle-to-cycle jitter measured on the DLL output clock, excluding input clock jitter.
Phase Offset between CLKIN and CLKO is the worst-case fixed time difference between rising edges of CLKIN and CLKO,
excluding output jitter and input clock jitter.
Phase Offset between Clock Outputs on the DLL is the worst-case fixed time difference between rising edges of any two DLL
outputs, excluding output jitter and input clock jitter.
Maximum Phase Difference between CLKIN and CLKO is the sum of output jitter and phase offset between CLKIN and CLKO, or
the greatest difference between CLKIN and CLKO rising edges due to DLL alone (excluding input clock jitter).
Maximum Phase Difference between Clock Outputs on the DLL is the sum of output jitter and phase offset between any DLL
clock outputs, or the greatest difference between any two DLL output rising edges due to DLL alone (excluding input clock jitter).
PHIO
F
F
Symbol
T
CLKINHF
CLKINLF
DLLPW
R
Input clock period tolerance
Input clock jitter tolerance (cycle-to-cycle)
Time required for DLL to acquire lock
Output jitter (cycle-to-cycle) for any DLL clock output
Phase offset between CLKIN and CLKO
Phase offset between clock outputs on the DLL
Phase difference between CLKIN and CLKO
Phase difference between clock outputs on the DLL
Input clock frequency (CLKDLLHF)
Input clock frequency (CLKDLL)
Input clock pulse width
Description
Description
(1)
(3)
www.xilinx.com
Spartan-IIE FPGA Family: DC and Switching Characteristics
(5)
(4)
≥100 MHz
≥150 MHz
≥200 MHz
≥250 MHz
≥300 MHz
worst-case values across the recommended operating con-
ditions.
Figure 22, page
ters in the table below.
≥25 MHz
≥50 MHz
F
50-60 MHz
40-50 MHz
30-40 MHz
25-30 MHz
(6)
> 60 MHz
CLKIN
(2)
F
-
-
CLKIN
Min
5.0
3.0
2.4
2.0
1.8
1.5
1.3
60
25
44, provides definitions for various parame-
CLKDLLHF
Min
-
-
-
-
-
-
-
-
-
-
-
-
-7
Speed Grade
Max
320
160
-
-
-
-
-
-
-
±150
±100
±140
±160
± 200
Max
± 60
1.0
20
-
-
-
-
Min
5.0
3.0
2.4
2.0
1.8
1.5
NA
60
25
Min
CLKDLL
-
-
-
-
-
-
-
-
-
-
-
-
-6
± 300
± 200
±100
±140
±160
Max
Max
275
135
± 60
120
1.0
20
25
50
90
-
-
-
-
-
-
-
Units
Units
MHz
MHz
ns
ps
μs
μs
μs
μs
μs
ps
ps
ps
ps
ps
ns
ns
ns
ns
ns
ns
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