XC2S600E-6FG676C Xilinx Inc, XC2S600E-6FG676C Datasheet - Page 23

• Manufacturer Part Number: XC2S600E-6FG676C
• Description: FPGA Spartan-IIE Family 600K Gates 15552 Cells 357MHz 0.15um Technology 1.8V 676-Pin FBGA
• Manufacturer: Xilinx Inc

Specifications of XC2S600E-6FG676C

• Package: 676FBGA
• Family Name: Spartan-IIE
• Device Logic Cells: 15552
• Device Logic Units: 3456
• Device System Gates: 600000
• Maximum Internal Frequency: 357 MHz
• Typical Operating Supply Voltage: 1.8 V
• Maximum Number Of User I/os: 514
• Ram Bits: 294912
• Re-programmability Support: Yes

DS077-2 (v2.3) June 18, 2008
Product Specification
Figure 16: Configuration Flow Diagram
Configuration
at Power-up
V
R
High?
V
AND
CCINT
CCO
Yes
FPGA Drives DONE High,
Start-up Sequence
Releases GSR net
and DONE Low
User Operation
Activates I/Os,
Configuration
Configuration
Data Frames
User Holding
Drives INIT
User Holding
Mode Pins
No
PROGRAM
Correct?
Samples
Memory
No
FPGA
FPGA
Clear
CRC
Load
Low?
Low?
INIT
No
Yes
No
Yes
Yes
Configuration During
User Operation
PROGRAM
Abort Start-up
User Pulls
FPGA Drives
INIT Low
Delay
Configuration
Delay
Configuration
Low
DS001_11_111501
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Clearing Configuration Memory
The device indicates that clearing the configuration memory
is in progress by driving INIT Low.
Delaying Configuration
At this time, the user can delay configuration by holding
either PROGRAM or INIT Low, which causes the device to
remain in the memory clearing phase. Note that the bidirec-
tional INIT line is driving a Low logic level during memory
clearing. Thus, to avoid contention, use an open-drain driver
to keep INIT Low.
With no delay in force, the device indicates that the memory
is completely clear by driving INIT High. The FPGA samples
its mode pins on this Low-to-High transition.
Loading Configuration Data
Once INIT is High, the user can begin loading configuration
data frames into the device. The details of loading the con-
figuration data are discussed in the sections treating the
configuration modes individually. The sequence of opera-
tions necessary to load configuration data using the serial
modes is shown in
Parallel mode is shown in
CRC Error Checking
After the loading of configuration data, a CRC value embed-
ded in the configuration file is checked against a CRC value
calculated within the FPGA. If the CRC values do not
match, the FPGA drives INIT Low to indicate that an error
has occurred and configuration is aborted. Note that
attempting to load an incorrect bitstream causes configura-
tion to fail and can damage the device.
To reconfigure the device, the PROGRAM pin should be
asserted to reset the configuration logic. Recycling power
also resets the FPGA for configuration. See
figuration
Start-up
The start-up sequence oversees the transition of the FPGA
from the configuration state to full user operation. A match
of CRC values, indicating a successful loading of the config-
uration data, initiates the sequence.
Spartan-IIE FPGA Family: Functional Description
Memory.
Figure
18. Loading data using the Slave
Figure 21, page
28.
Clearing Con-
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