XC2V4000-4FF1152C Xilinx Inc, XC2V4000-4FF1152C Datasheet - Page 91

• Manufacturer Part Number: XC2V4000-4FF1152C
• Description: FPGA Virtex-II Family 4M Gates 51840 Cells 650MHz 0.15um/0.12um (CMOS) Technology 1.5V 1152-Pin FCBGA
• Manufacturer: Xilinx Inc

Specifications of XC2V4000-4FF1152C

• Package: 1152FCBGA
• Family Name: Virtex-II
• Device Logic Units: 51840
• Device System Gates: 4000000
• Number Of Registers: 46080
• Maximum Internal Frequency: 650 MHz
• Typical Operating Supply Voltage: 1.5 V
• Maximum Number Of User I/os: 824
• Ram Bits: 2211840
• Re-programmability Support: Yes
• Case: BGA
• Dc: 05+

DS031-3 (v3.5) November 5, 2007
Product Specification
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06/24/04
03/01/05
Date
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Version
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3.3
3.4
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Table
Updated values in
Characteristics
Table 34
specified a capacitive load parameter.
Figure 1: Added note to figure regarding termination resistors.
Table
junction temperature”.
In section
11713 with reference to
outputs (SSO).
In section
-
-
-
-
Table
now available in these tables.
XC2V8000 is no longer offered in the -6 speed grade. The following tables containing
parameters or other references to this device/grade combination were corrected
accordingly:
Table
Table
Footnote (2) to new Footnote (3).
Table
-
-
Section
statement that power supplies can be turned on in any sequence.
Added section
diagrams as well as parameter specification tables formerly included in the
Platform FPGA User Guide
Table
(Global Clock Buffer S Input Setup/Hold to I1 and I2 Inputs).
Table
parameters.
Recompiled for backward compatibility with Acrobat 4 and above.
Table
Updated values in
Characteristics
Table
battery is not used.
Table
Section
description of supply voltage ramp-on requirements. Added sentence to footnote (1)
indicating that if the stated requirements are violated, no damage to the device will
result, but configuration will probably fail.
Figure 3
CCLK.
Table 18
Added new
Replaced
Revised and extended text describing output delay measurement procedure.
For XC2V40, added Maximum quiescent supply current specifications.
For all devices, updated Typical specifications for I
13: All Virtex-II devices and speed grades now Production.
1: Changed T
45,
47, and
39: For Input Clock Low/High Pulse Width, PSCLK and CLKIN, changed existing
4:
20,
38,
1: Added T
2: Corrected Footnote (1) to require connecting V
3: Corrected "V
Power-On Power Supply Requirements, page
Power-On Power Supply
and
and
Table
Clock Distribution Switching
Operating Frequency
General Power Supply
I/O Standard Adjustment Measurement
Table
renamed
Figure
Table
Table
Figure
Configuration Timing, page
tables, based on values extracted from speedsfile version 1.116.
tables, based on values extracted from speedsfile version 1.120.
47, and
Table
SOL
www.xilinx.com
Virtex-II Performance Characteristics
13,
Virtex-II Performance Characteristics
35: Revised test setup footnote to refer to
J
48.
4: Corrected to show DOUT transitions driven by falling edge of
description from “Operating junction temperature” to “Maximum
1,
parameters for Pb-free package devices.
REF
19,
Table
Input Delay Measurement
Virtex-II Platform FPGAs: DC and Switching Characteristics
Generalized Test
Table
XAPP689
current per bank" to "V
Output Delay Measurement
.
14,
48: All Source-Synchronous parameters for all devices
Ranges: Added Footnote (4) to all four CLKIN
Table
Requirements: Added word “monotonically” to
Requirements, replaced reference to Answer Record
regarding handling of simultaneously switching
Revision
34,
Characteristics: Added parameter T
Setup, with new drawing.
Table
27. This section includes new timing
35,
REF
Methodology. Added footnotes.
Methodology:
Table
current per pin."
Methodology.
3: Added Footnote (1) qualifying
CCINTQ
BATT
and
and
36,
to V
Virtex-II Switching
Virtex-II Switching
Figure
Table
and I
CCAUX
CCAUXQ
37,
1. Previously
Table
or GND if
GSI
.
Virtex-II
Module 3 of 4
/T
45,
GIS
43