XC2V4000-4FF1152C Xilinx Inc, XC2V4000-4FF1152C Datasheet - Page 68

• Manufacturer Part Number: XC2V4000-4FF1152C
• Description: FPGA Virtex-II Family 4M Gates 51840 Cells 650MHz 0.15um/0.12um (CMOS) Technology 1.5V 1152-Pin FCBGA
• Manufacturer: Xilinx Inc

Specifications of XC2V4000-4FF1152C

• Package: 1152FCBGA
• Family Name: Virtex-II
• Device Logic Units: 51840
• Device System Gates: 4000000
• Number Of Registers: 46080
• Maximum Internal Frequency: 650 MHz
• Typical Operating Supply Voltage: 1.5 V
• Maximum Number Of User I/os: 824
• Ram Bits: 2211840
• Re-programmability Support: Yes
• Case: BGA
• Dc: 05+

Clock Distribution Switching Characteristics
Table 20: Clock Distribution Switching Characteristics
CLB Switching Characteristics
Delays originating at F/G inputs vary slightly according to the input used (see
are worst-case. Precise values are provided by the timing analyzer.
Table 21: CLB Switching Characteristics
DS031-3 (v3.5) November 5, 2007
Product Specification
Global Clock Buffer I input to O output
Global Clock Buffer S input Setup/Hold
to I1 an I2 inputs
Combinatorial Delays
Sequential Delays
Setup and Hold Times Before/After Clock CLK
Clock CLK
Set/Reset
4-input function: F/G inputs to X/Y outputs
5-input function: F/G inputs to F5 output
5-input function: F/G inputs to X output
FXINA or FXINB inputs to Y output via MUXFX
FXINA input to FX output via MUXFX
FXINB input to FX output via MUXFX
SOPIN input to SOPOUT output via ORCY
Incremental delay routing through transparent latch to
XQ/YQ outputs
FF Clock CLK to XQ/YQ outputs
Latch Clock CLK to XQ/YQ outputs
BX/BY inputs
DY inputs
DX inputs
CE input
SR/BY inputs (synchronous)
Minimum Pulse Width, High
Minimum Pulse Width, Low
Minimum Pulse Width, SR/BY inputs (asynchronous)
Delay from SR/BY inputs to XQ/YQ outputs
(asynchronous)
Toggle Frequency (MHz) (for export control)
R
Description
Description
www.xilinx.com
Virtex-II Platform FPGAs: DC and Switching Characteristics
T
T
T
T
T
T
Symbol
DXCK
CECK
SRCK/
DYCK
DICK
Symbol
T
GSI
T
T
T
T
SOPSOP
T
T
T
T
T
F
IFNCTL
T
T
INAFX
INBFX
T
T
GIO
T
CKLO
IFXY
RPW
IF5X
CKO
TOG
/T
ILO
IF5
CH
RQ
CL
/T
/T
/T
/T
T
GIS
SCKR
CKDI
CKDY
CKDX
CKCE
Figure 16
0.55/ 0
0.30/–0.07
0.30/–0.07
0.30/–0.07
0.19/–0.06
0.21/–0.02
0.47
-6
0.35
0.57
0.76
0.36
0.26
0.26
0.35
0.41
0.45
0.54
0.61
0.61
0.61
1.06
820
-6
Speed Grade
in Module 2). The values listed below
Speed Grade
0.61/ 0
0.33/–0.08
0.33/–0.08
0.33/–0.08
0.21/–0.07
0.23/–0.03
0.52
-5
0.39
0.63
0.83
0.39
0.28
0.28
0.38
0.45
0.50
0.59
0.67
0.67
0.67
1.17
750
-5
0.70/ 0
0.37/–0.09
0.37/–0.09
0.37/–0.09
0.24/–0.08
0.26/–0.03
0.59
-4
0.44
0.72
0.95
0.45
0.32
0.32
0.44
0.51
0.57
0.68
0.77
0.77
0.77
1.34
650
-4
Module 3 of 4
ns, Max
ns, Max
Units
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
Units
MHz
20