A1460A-1PQ208C Actel, A1460A-1PQ208C Datasheet - Page 8

• Manufacturer Part Number: A1460A-1PQ208C
• Description: FPGA ACT 3 Family 6K Gates 848 Cells 125MHz 0.8um (CMOS) Technology 5V 208-Pin PQFP
• Manufacturer: Actel

Specifications of A1460A-1PQ208C

• Package: 208PQFP
• Family Name: ACT 3
• Device Logic Gates: 6000
• Device Logic Units: 848
• Device System Gates: 15000
• Number Of Registers: 768
• Maximum Internal Frequency: 125 MHz
• Typical Operating Supply Voltage: 5 V
• Maximum Number Of User I/os: 167
• Maximum Propagation Delay Time: 2.6 ns

The S-module contains a full implementation of the C-module
plus a clearable sequential element that can either
implement a latch or flip-flop function. The S-module can
therefore implement any function implemented by the
C-module. This allows complex combinatorial-sequential
functions to be implemented with no delay penalty. The
Designer Series Development System will automatically
combine any C-module macro driving an S-module macro into
the S-module, thereby freeing up a logic module and
eliminating a module delay.
The clear input CLR is accessible from the routing channel.
In addition, the clock input may be connected to one of three
clock networks: CLKA, CLKB, or HCLK. The C-module and
S-module functional descriptions are shown in Figures 2
and 3. The clock selection is determined by a multiplexor
select at the clock input to the S-module.
I/Os
I/O Modules
I/O modules provide an interface between the array and the
I/O Pad Drivers. I/O modules are located in the array and
access the routing channels in a similar fashion to logic
modules. The I/O module schematic is shown in Figure 4. The
signals DataIn and DataOut connect to the I/O pad driver.
Each I/O module contains two D-type flip-flops. Each flip-flop
is connected to the dedicated I/O clock (IOCLK). Each
flip-flop can be bypassed by nonsequential I/Os. In addition,
each flip-flop contains a data enable input that can be
accessed from the routing channels (ODE and IDE). The
asynchronous preset/clear input is driven by the dedicated
Figure 3 • S-Module Diagram
1-182
D10
D11
D00
D01
A1 B1
S1
A0 B0
S0
Y
CLK
Figure 2 • C-Module Diagram
preset/clear network (IOPCL). Either preset or clear can be
selected individually on an I/O module by I/O module basis.
The I/O module output Y is used to bring Pad signals into the
array or to feed the output register back into the array. This
allows the output register to be used in high-speed state
machine applications. Side I/O modules have a dedicated
output segment for Y extending into the routing channels
above and below (similar to logic modules). Top/Bottom I/O
modules have no dedicated output segment. Signals coming
into the chip from the top or bottom are routed using F-fuses
and LVTs (F-fuses and LVTs are explained in detail in the
routing section).
D
CLR
Q
D10
D00
D01
A1 B1
D11
S1
OUT
A0 B0
S0
Y
OUT