A1460A-1PQ208C Actel, A1460A-1PQ208C Datasheet - Page 2

• Manufacturer Part Number: A1460A-1PQ208C
• Description: FPGA ACT 3 Family 6K Gates 848 Cells 125MHz 0.8um (CMOS) Technology 5V 208-Pin PQFP
• Manufacturer: Actel

Specifications of A1460A-1PQ208C

• Package: 208PQFP
• Family Name: ACT 3
• Device Logic Gates: 6000
• Device Logic Units: 848
• Device System Gates: 15000
• Number Of Registers: 768
• Maximum Internal Frequency: 125 MHz
• Typical Operating Supply Voltage: 5 V
• Maximum Number Of User I/os: 167
• Maximum Propagation Delay Time: 2.6 ns

Des crip tion
Actel’s ACT 3 Accelerator Series of FPGAs offers the
industry’s fastest high-capacity programmable logic device.
ACT 3 FPGAs offer a high perfomance, PCI compliant
programmable solution capable of 250 MHz on-chip
performance and 7.5 nanosecond clock-to-output, with
capacities spanning from 1,500 to 10,000 gate array
equivalent gates. For further information regarding PCI
compliance of ACT 3 devices, see “Accelerator Series
FPGAs—ACT 3 PCI Compliant Family.”
The ACT 3 family builds on the proven two-module
architecture consisting of combinatorial and sequential logic
modules used in Actel’s 3200DX and 1200XL families. In
addition, the ACT 3 I/O modules contain registers which
deliver 7.5 nanosecond clock-to-out times.
contain four clock distribution networks, including dedicated
array and I/O clocks, supporting very fast synchronous and
asynchronous designs. In addition, routed clocks can be used
to drive high fanout signals such as flip-flop resets and output
enables.
Sys tem Pe rf ormance Mo del
1-176
A1425A-3
A1460A-3
I/O CLK
I/O Module
Chip #1
t
CKHS
7.5
9.0
t
CKHS
The devices
Chip-to-Chip Performance
t
(Worst-Case Commercial)
TRACE
1.0
1.0
t
TRACE
The ACT 3 family is supported by Actel’s Designer Series
Development System which offers automatic placement and
routing (with automatic or fixed pin assignments), static
timing anlaysis, user programming, and debug and diagnostic
probe capabilities. The Designer Series is supported on the
following platforms: 486/Pentium class PC’s, Sun
workstations.
Cadence, Mentor Graphics
design environments. Additional platforms are supported
through Actel’s Industry Alliance Program, including DATA
I/O (ABEL FPGA) and MINC.
Predictable Performance* (Worst-Case Commercial)
Accumulators (16-bit)
Loadable Counters (16-bit)
Prescaled Loadable Counters (16-bit)
Shift Registers
35 pF
t
INSU
1.8
1.3
I/O CLK
The software provides CAE interfaces to
t
INSU
10.3 ns
11.3 ns
I/O Module
Total
Chip #2
®
63 MHz
, OrCAD
110 MHz
™
and Viewlogic
250 MHz
250 MHz
MHz
®
97
88
‚ and HP
®
®
‚
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