CN8237EBGB Mindspeed Technologies, CN8237EBGB Datasheet - Page 312

• Manufacturer Part Number: CN8237EBGB
• Description: ATM SAR 622Mbps 3.3V ABR/CBR/GFR/UBR/VBR 456-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8237EBGB

• Package: 456BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 622 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3.135 V

14.0 CN8237 Registers
14.5 Reassembly Registers
0x1f0
0x1f8
14-22
31–16
31–16
15–14
15–0
11–8
7–0
Bit
Bit
13
12
—
—
Reassembly Free Buffer Queue Base Register (RSM_FQBASE)
Reassembly Free Buffer Queue Control Register (RSM_FQCTRL)
Field
Field
Size
Size
16
16
16
2
1
1
4
8
FBQ1_BASE
FBQ0_BASE
Reserved
FBQ_SIZE
FWD_RND
FBQ0_RTN
FWD_EN
FBQ_UD_INT
Name
This register determines the base address of both banks of contiguous free buffer
queue spaces. The base address is a 16-bit number. Since both banks reside in
SAR-shared memory (23-bits of byte addressing), the structures can start on
128 byte boundaries. Bank 0 has additional boundary requirements if the buffer
return mechanism is enabled.
This register contains free buffer queue control information.
Name
Mindspeed Technologies
Not implemented at this time.
Free Buffer Queue Size. Selects the size of all free buffer queues.
0 = 64
1 = 256
2 = 1,024
3 = 4,096
Buffer Return Processing Priority Selection. When a logic low, buffer return
entries are processed from queues in priority fashion with queue 15 having
the highest priority. When a logic high, round-robin arbitration is used.
Free Buffer Queue 0 Buffer Return Enable. When a logic high, bank 0 is
enabled to process buffer return for firewall operation. When this bit is set,
queue entries 0–15 are four words independent of the value of FWD_EN;
otherwise, they are two words.
Forward Processing Enable. Selects the number of free buffer queues in bank
0 that have buffer return processing enabled. Starting with free buffer queue
0, a value of 0 in FWD_EN selects only one queue, and a value of 15 selects
16 queues.
Free Buffer Queue Update Interval. This value determines how many buffers
are taken off the free buffer queue before the reassembly coprocessor writes
the current read index pointer to host memory.
Free Buffer Queue Bank 0 base address.
Free Buffer Queue Bank 1 base address.
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
™
Description
Description
28237-DSH-001-C
CN8237