DS21Q55N Maxim Integrated Products, DS21Q55N Datasheet - Page 4

• Manufacturer Part Number: DS21Q55N
• Description: Framer E1/J1/T1 3.3V 256-Pin BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS21Q55N

• Package: 256BGA
• Number Of Transceivers: 4
• Standard Framing Format: E1|J1|T1
• Maximum Supply Current: 75(Typ) mA
• Minimum Single Supply Voltage: 3.135 V
• Maximum Single Supply Voltage: 3.465 V

22.
23.
24.
25.
26.
27.
28.
29.
21.3
21.4
21.5
21.6
22.1
22.2
22.3
22.4
22.5
22.6
22.7
22.8
22.9
24.1
24.2
24.3
24.4
24.5
24.6
25.1
26.1
26.2
21.3.1 Receive ....................................................................................................135
21.3.2 Transmit ...................................................................................................137
21.3.3 FIFO Information ......................................................................................142
21.3.4 Receive Packet-Bytes Available ...............................................................142
21.3.5 HDLC FIFOs ............................................................................................143
21.5.1 Overview ..................................................................................................144
21.5.2 Receive Section .......................................................................................144
21.5.3 Transmit Section ......................................................................................146
22.2.1 Receive Level Indicator and Threshold Interrupt ......................................148
22.2.2 Receive G.703 Synchronization Signal (E1 Mode) ...................................148
22.2.3 Monitor Mode ...........................................................................................148
22.3.1 Transmit Short-Circuit Detector/Limiter ....................................................149
22.3.2 Transmit Open-Circuit Detector................................................................149
22.3.3 Transmit BPV Error Insertion....................................................................149
22.3.4 Transmit G.703 Synchronization Signal (E1 Mode) ..................................149
25.1.1 Number-of-Errors Left Register ................................................................186
LINE INTERFACE UNIT (LIU) ...................................................................................................147
PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION .......................166
BERT FUNCTION......................................................................................................................173
PAYLOAD ERROR-INSERTION FUNCTION (T1 MODE ONLY) ..............................................183
INTERLEAVED PCM BUS OPERATION (IBO).........................................................................187
EXTENDED SYSTEM INFORMATION BUS (ESIB)..................................................................190
PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER .....................................................194
FRACTIONAL T1/E1 SUPPORT ...............................................................................................195
HDLC M
R
L
D4/SLC-96 O
LIU O
R
T
MCLK P
J
CMI (C
LIU C
R
C
S
M
BERT R
BERT R
BERT B
BERT E
N
C
F
ITTER
EGACY
RANSMITTER
RAME
TATUS
ECEIVE
ECEIVER
ECOMMENDED
OMPONENT
UMBER
HANNEL
APPING
ONTROL
PERATION
A
ODE
I
.........................................................................................................173
NTERLEAVE
FDL S
IT
RROR
-
RESCALER
EGISTER
EPETITIVE
TTENUATOR
APPING
HDLC C
.......................................................................................................173
OF
I
.....................................................................................................147
C
NTERLEAVE
-E
M
OUNTER
S
................................................................................................149
PERATION
ARK
RRORS
R
C
PECIFICATIONS
UPPORT
.............................................................................................147
EGISTERS
C
OUNTER
............................................................................................135
D
ODE
IRCUITS
I
P
NVERSION
ESCRIPTIONS
........................................................................................150
.......................................................................................187
ATTERN
......................................................................................150
......................................................................................180
R
...................................................................................187
E
EGISTERS
(T1 M
.................................................................................146
XAMPLE
................................................................................181
..............................................................................151
..............................................................................160
S
) O
ODE
........................................................................162
ET
PTION
....................................................................144
....................................................................175
...................................................................179
) ................................................................144
..................................................................185
...........................................................150
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