DS21Q55N Maxim Integrated Products, DS21Q55N Datasheet - Page 198

• Manufacturer Part Number: DS21Q55N
• Description: Framer E1/J1/T1 3.3V 256-Pin BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS21Q55N

• Package: 256BGA
• Number Of Transceivers: 4
• Standard Framing Format: E1|J1|T1
• Maximum Supply Current: 75(Typ) mA
• Minimum Single Supply Voltage: 3.135 V
• Maximum Single Supply Voltage: 3.465 V

30.
30.1 Description
The DS2Q155 IEEE 1149.1 design supports the standard instruction codes SAMPLE/PRELOAD,
BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE
(Figure
access port (TAP) and boundary scan architecture.
§ Test Access Port
§ TAP Controller
§ Instruction Register
§ Bypass Register
§ Boundary Scan Register
§ Device Identification Register
The TAP contains the necessary interface pins JTRST, JTCLK, JTMS, JTDI, and JTDO. See the pin
descriptions in Section
Figure 30-1. JTAG Functional Block Diagram
JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT
30-1.). The DS21Q55 contains the following features as required by IEEE 1149.1 standard test
2
10kΩ
for details.
+V
JTDI
10kΩ
+V
JTMS
TEST ACCESS PORT
BOUNDARY SCAN
IDENTIFICATION
CONTROLLER
INSTRUCTION
REGISTER
REGISTER
REGISTER
REGISTER
BYPASS
JTCLK
198 of 237
10kΩ
+V
JTRST
SELECT
OUTPUT ENABLE
MUX
JTDO