APA600-CQ208B Actel, APA600-CQ208B Datasheet - Page 35

• Manufacturer Part Number: APA600-CQ208B
• Description: FPGA ProASICPLUS Family 600K Gates 180MHz 0.22um (CMOS) Technology 2.5V 208-Pin CQFP
• Manufacturer: Actel

Specifications of APA600-CQ208B

• Package: 208CQFP
• Family Name: ProASICPLUS
• Device System Gates: 600000
• Number Of Registers: 21504
• Maximum Internal Frequency: 180 MHz
• Typical Operating Supply Voltage: 2.5 V
• Maximum Number Of User I/os: 158
• Ram Bits: 129024
• Re-programmability Support: Yes

Design Environment
The ProASIC
both Actel's Libero
(IDE) and Designer FPGA Development software. Actel
Libero IDE is an integrated design manager that
seamlessly integrates design tools while guiding the user
through the design flow, managing all design and log
files, and passing necessary design data among tools.
Additionally, Libero IDE allows users to integrate both
schematic and HDL synthesis into a single flow and verify
the entire design in a single environment (see Actel’s
website for more information about
IDE includes Synplify
AE from Mentor Graphics
from Mentor Graphics, WaveFormer Lite™ AE from
SynaptiCAD
Magma, and Designer software from Actel.
PALACE is an effective tool when designing with
ProASIC
takes an EDIF netlist and optimizes the performance of
ProASIC
process, ensuring that timing closure is easily achieved.
Actel's Designer software is a place-and-route tool that
provides a comprehensive suite of backend support tools
for FPGA development. The Designer software includes
the following:
• Timer – A world-class integrated static timing
• NetlistViewer – A design netlist schematic viewer
• ChipPlanner – A graphical floorplanner viewer and
• SmartPower – Allows the designer to quickly
• PinEditor – A graphical application for editing pin
• I/O Attribute Editor – Displays all assigned and
analyzer and constraints editor that supports
timing-driven place-and-route
editor
estimate the power consumption of a design
assignments and I/O attributes
unassigned I/O macros and their attributes in a
spreadsheet format
PLUS
PLUS
. PALACE AE Physical Synthesis from Magma
®
devices through a physical placement-driven
PLUS
, PALACE™ AE Physical Synthesis from
family of FPGAs is fully supported by
®
®
AE from Synplicity®, ViewDraw
Integrated Design Environment
®
, ModelSim
Libero
®
HDL Simulator
IDE). Libero
®
v5.9
With the Designer software, a user can lock the design
pins before layout while minimally impacting the results
of place-and-route. Additionally, Actel’s back-annotation
flow is compatible with all the major simulators. Another
tool included in the Designer software is the SmartGen
macro builder, which easily creates popular and
commonly used logic functions for implementation into
your schematic or HDL design.
Actel's Designer software is compatible with the most
popular FPGA design entry and verification tools from
EDA vendors, such as Mentor Graphics, Synplicity,
Synopsys, and Cadence Design Systems. The Designer
software is available for both the Windows and UNIX
operating systems.
ISP
The user can generate *.bit or *.stp programming files
from the Designer software and can use these files to
program a device.
ProASIC
more information on ISP of ProASIC
the
Performing Internal In-System Programming Using Actel’s
ProASIC
programmed for the first time, the ProASIC
are in a tristate condition with the pull-up resistor option
enabled.
In-System Programming ProASIC
PLUS
PLUS
devices can be programmed in-system. For
Devices
application notes. Prior to being
ProASIC
PLUS
PLUS
Flash Family FPGAs
PLUS
devices, refer to
PLUS
Devices
device I/Os
2-25
and