ISL5216KI-1 Intersil, ISL5216KI-1 Datasheet
ISL5216KI-1
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ISL5216KI-1 Summary of contents
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... ISL5216KI-1 ISL5216KIZ (Note) ISL5216KIZ ISL5216KI-1Z (Note) ISL5216KI-1Z NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 ...
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Block Diagram μP TEST REGISTER INPUT SELECT, FORMAT, DEMUX A(15:-1) INPUT SELECT, FORMAT, ENIA DEMUX B(15:-1) ENIB INPUT SELECT, FORMAT, DEMUX C(15:-1) ENIC INPUT SELECT, FORMAT, DEMUX D(15:-1) ENID INPUT SELECT, FORMAT, DEMUX CLK RESET SYNCI SYNCO SYNCI0 SYNCI1 P(15:0) ...
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Pinout B15 A0 B14 E B13 GND B12 F B11 VCC1 B10 G B9 GND GND H CLK VCC2 GND B6 ...
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Pin Descriptions NAME TYPE POWER SUPPLY Positive Power Supply Voltage (core), 2.5V ±0.125 VCC1 - Positive Power Supply Voltage (I/O), 3.3V ±0.165 VCC2 - GND - Ground, 0V. INPUTS A(15:0), Am1 I Parallel Data Input bus A. Sampled on the ...
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Pin Descriptions (Continued) NAME TYPE SYNCI3 I Synchronization input signal for channel 3. Same functions as SYNCI but connects only to channel 3. This pin is internally pulled low to allow left unconnected. SYNCO O Synchronization Output ...
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Pin Descriptions (Continued) NAME TYPE Microprocessor Interface Read or Read/Write Signal. When the Microprocessor Interface Mode Control, μ MODE low the data from the address specified is placed on P(15:0) when RD is asserted (low) ...
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Input Select/Format Block TEST ENI SELECT (IWA *000 - 12 or GWA F804 - 12) μP TEST REGISTER 15:0 (GWA F807 - 15:0) TESTENBIT TESTEN (IWA *000 - 11 or GWA F804 - 11) TESTENSTRB (GWA F808) A(15:-1) ENIA B(15:-1) ...
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The floating point modes and the mapping of the parallel 17-bit input format is discussed below. Floating Point Input Mode Bit Mapping The input bit weighting for fixed point inputs on busses and D is: ...
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MODE: 13-BIT MANTISSA (15:3), 3-BIT EXPONENT (2:0), 18dB EXPONENT RANGE (Note 7) EXPONENT GAIN (dB) X(2:0) = 000 0 X15 X(2:0) = 001 6 X15 X(2:0) = 010 12 X15 X(2:0) = 011 18 X15 (Note 6) NOTES: 6. ...
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MODE: 15-BIT MANTISSA (15:1), 2-BIT EXPONENT (-1, 0), 18dB MAXIMUM EXPONENT RANGE (Note 12) EXPONENT GAIN (dB) 000 0 X15 001 6 X15 010 12 X15 011 18 X15 NOTE: 12. To select this mode, set IWA *000H/GWA F804H ...
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Complex Input Mode In this mode, complex (I/Q) data can be input using two clock cycles with I input first and Q input second. The ENIx signal indicates the clock cycle when I is valid. The Q data is taken ...
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The integrator bit widths are 69, 62, 53, 44, and 34 for the t first through fifth stages, respectively, while the comb bit widths are all 32. The integrators are sized for decimation factors 512 with five ...
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Back End Data Routing FROM CIC DESTINATION BIT MAP (BITS 28:18 OF FIR INSTRUCTIONS BIT FIELD AGC LOOP GAIN SELECT (PATH 01 ONLY) 27 UPDATE ...
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Filter Compute Engine R/dφ/dt RAM 384 WORDS 0..-23 I INMUX (1:0) Q RAMR/Wb ADDRA (8:0) ADDRB (8:0) COEF (21:0), SHIFT (1:0) The filter compute engine is a dual multiply-accumulator (MAC) data path with a ...
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IWA = *00Ah bits 11:0. The number and order of the filtering in the filter chain is defined by a FIR control program. The FIR control ...
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Sample filter #2 requires: • 128 + 8 = 200 data RAM locations • (95+1)/ coefficient RAM location (resampler and HBF coefficients are in ROM). The number of clock cycles required to compute an ...
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CIC decimation we have chosen. Each channel computes the same sequence, offset by one output sample from the previous sample (see IWA = *00Bh). Each channel decimates down to 2.048M ...
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Filter Sequencer NEW DATA, FIR # INSTRUCTION RAM, RESET SEQUENCER SYNC THRESHOLD DECREMENT 1 WAIT COUNTER DECREMENT 2 LOOP LOOP COUNTER COUNTER PRELOAD RESAMPLER NCO 18 ISL5216 FIR# - WRITE DESTINATION FIR# - COMPUTE READ ALIAS POINTER MASK DATA ADDRESS ...
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Instruction Bit Fields BIT POSITIONS FUNCTION 8:0 Instruction Instruction Field Bit Mapping Bit Type WAIT FIR JUMP (NOPs and loading the loop counter are special cases of the FIR instruction). 14:9 FIR Type FIR Parameter Bit Fields 14:9 000000 000001 ...
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BIT POSITIONS FUNCTION 28:18 Destination Destination Field Bit Mapping 28 AGCLFGN AGCLF AGCLFGN AGC loop gain select. Only applies to Path 1. AGCLF Path(1: F(4:0) 31:29 Round Select 31:29 000 001 010 011 100 101 110 111 Provided ...
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BIT POSITIONS FUNCTION 63 Reserved Set to 0. 66:64 Coefficient Memory 66:64 Block Size (Modulo addressing can be used, but is usually not needed. If not needed this bit field can always ...
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BIT POSITIONS FUNCTION 125:123 Coefficient Memory (ADDRC) Usually set to 0. Block-to-Block Step 125:123 127:126 Reserved Set to 0 Basic Instruction Set Examples 1. Wait for number of input samples > threshold ...
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Wait Preload Register This register (IWA register *00Ch) holds the wait counter threshold and two wait counter decrement values. Each is ten bits. The wait counter counts filter input samples until the count is greater than or equal to the ...
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FIR filter output into the range of 20-bit and shorter words in the output section. Without gain control, -12 a signal at -72dBFS = 20log ( the input would have 10 only 4 bits of resolution ...
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In dB, this can be expressed as: (AGC Mult/Shift Gain) log (2 10 The full AGC range of the multiplier/shifter is from 0dB to 14 -14 20log [ -1 20log 10 10 The 16 ...
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The loop gain mantissas and exponents are set in IWA register *010h, with IWA register *013h selecting loop gain and the settling mode. In the ISL5216, a SYNCI signal will clear the AGC loop filter accumulator if ...
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Table 1 details the phase and magnitude weighting for the 16 bits output from the PDC. TABLE 1. MAG/PHASE BIT WEIGHTING BIT MAGNITUDE 2 23 (MSB ...
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Serial Data Output Formatter Section ZERO I1 Q1 MAG R E PHASE GAIN STROBE ZERO NOTE: Each serial output has 7 time slots. Each slot can contain I1, Q1, I2, Q2, Mag, phase or dφ/dt, AGC gain, ...
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SD1 serial outputs). Any of seven types of data or zeros can be ...
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Microprocessor Interface 15:0 31: P(15: A(2: CLK CE (GATING NOT SHOWN) Data reads can be direct, indirect ...
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Read/Write Procedures To Write to the Internal Registers: 1. Load the indirect write holding registers at direct address ADD(2: and 1 with the data for the internal register ( bits depending on the internal register ...
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JTAG JTAG: The IEEE1149.1 Joint Test Action Group boundary scan standard operational codes shown in Table 3 below are supported. A separate application note is available with implementation details. TABLE 3. JTAG OP CODES SUPPORTED INSTRUCTION EXTEST IDCODE SAMPLE/PRELOAD INTEST ...
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TABLE OF MICROPROCESSOR DIRECT READ/WRITE ADDRESSES ADD(2:0) PINS 0 WR Indirect Write Holding Register, Bits 15: Indirect Write Holding Register, Bits 31:16 Indirect Write Address Register for Internal Target Register (Generates a write strobe to transfer ...
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Tables of Indirect Write Address (IWA) Registers NOTE: These Indirect Write Addresses are repeated for each channel. In the addresses below, the * field is the channel select nibble. These bits of the Indirect Address select the target channel TABLE ...
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TABLE 4. CHANNEL INPUT SELECT/FORMAT REGISTER (IWA = *000h) (Continued) P(31:0) 6:4 De-multiplex control. These control bits are provided to select a channel from a group of multiplexed channels eight multiplexed data streams can be demultiplexed. These control ...
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TABLE 7. CIC DECIMATION FACTOR REGISTER (IWA = *002h) P(15:0) 15:0 Load with the desired CIC decimation factor minus 1. TABLE 8. CIC DESTINATION FIR AND OUTPUT ENABLE/DISABLE REGISTER (IWA = *003h) P(15:0) 15:6 5:1 CIC output destination (FIR # ...
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TABLE 11. CARRIER NCO CENTER FREQUENCY UPDATE STROBE REGISTER (IWA = *006h) P(15:0) N/A Writing to this address generates a strobe that transfers the CCF value to the active frequency register. The transfer to the active register can also be ...
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TABLE 15. FILTER COMPUTE ENGINE/RESAMPLER CONTROL REGISTER (IWA = *00Ah) (Continued) P(31:0) 14 Enable RS freq offset. This bit, when set, enables the serially loaded resampler offset frequency word. When zero, the offset is zeroed. To disable the shifting, see ...
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TABLE 20. AGC GAIN READ STROBE REGISTER (IWA = *00Fh) P(15:0) 15:0 Writing to this location will sample the AGC loop filter output (forward gain value) to stabilize it for reading. The value is read from for RD; this location ...
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TABLE 25. SERIAL DATA OUTPUT CONTROL REGISTER (IWA = *014h) P(31:0) 31:29 Set to zero. 28 Sync polarity 1 Active low (low for one serial clock per word with a sync). 0 Active high. 27:26 Reserved, set to zero. 25:24 ...
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TABLE 26. SERIAL DATA OUTPUT 1 CONTENT/FORMAT REGISTER 1 (IWA = *015h) P(31:0) 31:24 Fourth serial slot in Serial Data Output 1 (SD1x See bits 7:0 for functional description of bits 31:24. 23:16 ...
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TABLE 28. SERIAL DATA OUTPUT 2 CONTENT/FORMAT REGISTER 1 (IWA = *017h) P(31:0) 31:24 Fourth serial slot in Serial Data Output 2 (SD2x See bits 7:0 of Table 26 for functional description of ...
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TABLE 34. FILTER COMPUTE ENGINE INSTRUCTION RAMS (IWA = *100h THRU *17Fh) P(31:0) 31:0 These locations in RAM are used to store the Filter Compute Engine instruction words. There are 128 bits per instruction word with each word consisting of ...
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TABLE 38. BUS ROUTING CONTROL REGISTER (GWA = F801h) P(31:0) 31:24 Unused - set to zero. 23:20 Interrupt pulse width. The width of the interrupt pulse at the pin can be programmed to be from clocks wide. ...
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TABLE 40. SERIAL CLOCK CONTROL REGISTER (GWA = F803h) P(15:0) 5 When set to 1, this bit will keep the serial clock disabled after a hardware reset until receipt of the first SYNCI signal. 4 Enables resetting serial clock divider ...
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TABLE 41. INPUT LEVEL DETECTOR SOURCE SELECT/FORMAT REGISTER (GWA = F804h) (Continued) P(31:0) 9 Fixed/Floating point 0 Fixed point 1 Floating point. The 17-bit input bus is divided into mantissa bits and one to three exponent bits ...
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TABLE 45. μP/TEST INPUT BUS ENI REGISTER (GWA = F808h) P(15:0) A write to this location, generates and ENI strobe for the μP driven input port (when selected via bit 12 of IWA *000h). N/A P(15:0) N/A A write to ...
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TABLE 50. TABLE OF INDIRECT READ ADDRESS (IRA) REGISTERS (Continued) IRA BITS *003h 5:0 CIC Destination FIR and Output Enable/Disable *004h 19:0 Carrier NCO/CIC Control *005h 31:0 Active Carrier NCO Center Frequency. *007h 31:0 Timing NCO Frequency (upper 32 bits) ...
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Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Electrical Specifications V CC1 T = -40°C to +85°C Industrial A PARAMETER INPUT AND CONTROL TIMING (FIGURE 3) CLK Frequency CLK High (Note 25) CLK Low (Note 25) Setup Time - Data Inputs, Input Enables, SYNCI, SYNCI(0-3) to CLK High ...
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Electrical Specifications V CC1 T = -40°C to +85°C Industrial (Continued) A PARAMETER R/W Hold Time from Rising Edge of DSTRB SERIAL CLOCK OUTPUT TIMING (FIGURE 11) CLK to Serial Data, Sync and SCLK (Divide-by 2 thru 16 Modes) CLK ...
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Waveforms (Continued) CLK ADD(1:0) P(15:0) FIGURE 7. MICROPROCESSOR WRITE TIMING (μP MODE = ADD(1:0) P(15:0) FIGURE 8. MICROPROCESSOR READ TIMING (μP MODE = 0) 52 ISL5216 PSW PHW t ...
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Waveforms (Continued) CLK CE RD/WR ADD(1:0) P(15:0) DSTRB FIGURE 9. MICROPROCESSOR WRITE TIMING (μP MODE = 1) CE RD/WR ADD(1:0) P(15:0) DSTRB FIGURE 10. MICROPROCESSOR READ TIMING (μP MODE = 1) 53 ISL5216 R/WSF t PSR t ...
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Waveforms (Continued) CLK SCLK (/2 THRU /16) SYNC SDXX 54 ISL5216 SCLK (DIVIDE PDL t SKEW2 t SKEW1 t PD FIGURE 11. SERIAL OUTPUT TIMING 2.0V 0. FIGURE 12. OUTPUT RISE AND FALL ...
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ROMd FIR Filters - Response Curves 0.0 -1.0 -2.0 -3 -6.0 0.0 0.1 0.2 0 FIGURE 13. CIC PASSBAND ROLLOFF ( STAGES DECIMATION FACTOR, ...
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ROMd FIR Filters - Response Curves 0 -20 -40 -60 -80 -100 -120 FREQUENCY (RELATIVE TO f NOTE: There is a 65dB limitation in SNR using the Re-Sampler Filter. FIGURE 18. ...
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FREQUENCY 5TH ORDER f /R PASSBAND ALIAS <-200 0.01 -0.007 -199.564 0.02 -0.029 -169.041 0.03 -0.064 -151.023 0.04 -0.114 -138.129 0.05 -0.179 -128.048 0.06 -0.257 -119.749 0.07 -0.351 -112.683 0.08 -0.458 -106.522 0.09 -0.580 -101.054 0.10 -0.717 ...
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TABLE 51. CIC PASSBAND AND ALIAS LEVELS (Continued) FREQUENCY 5TH ORDER f /R PASSBAND ALIAS S 0.32 -7.578 -40.311 0.33 -8.078 -38.832 0.34 -8.596 -37.401 0.35 -9.133 -36.015 0.36 -9.688 -34.674 0.37 -10.262 -33.374 0.38 -10.854 -32.114 0.39 -11.467 -30.892 ...
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TABLE 52. DECIMATING HALFBAND FIR FILTER COEFFICIENTS DECIMATING HALFBAND #1 (DHBF #1, 7-TAP) (DHBF #2, 11-TAP) COEFF HEX DECIMAL HEX C0 FBFE40 - 0.031303406 00C250 C1 000000 0.000000000 000000 C2 240100 0.281280518 F9B930 C3 3FFE80 0.499954224 000000 C4 240100 0.281280518 ...
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TABLE 53. INTERPOLATING HALFBAND FIR FILTER COEFFICIENTS INTERPOLATING HALFBAND #2 (IHBF #2, 15-TAP) COEFF HEX C0 FFAA24 C1 000000 C2 032B60 C3 000000 C4 F07F40 C5 000000 C6 4CAB00 C7 800000 C8 4CAB00 C9 000000 C10 F07F40 C11 000000 C12 ...
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COEFF HEX DECIMAL C 0/191 004000 0.001953125 C 1/190 006910 0.003206253 C 2/189 007A90 0.003740311 C 3/188 008C90 0.004289627 C 4/187 009ED0 0.004846573 C 5/186 00B0E0 0.005397797 C 6/185 00C230 0.005926132 C 7/184 00D240 0.006416321 C 8/183 00E090 0.006853104 C ...
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TABLE 55. BIT WEIGHTING FOR AGC LOOP FEEDBACK PATH AGC GAIN ACCUM GAIN ERROR AGC LOOP BIT ERROR BIT FILTER GAIN POSITION INPUT WEIGHT (MANTISSA ...
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Feature Changes 1. Core voltage lowered from 3.3V to 2.5V for lower power operation (I/O supply voltage remains at 3.3V). Maximum speed increased from 70MHz to 80MHz. 2. Added JTAG boundary scan test pins. 3. Added readback capability to all ...
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... A1 CORNER D A1 CORNER I.D. TOP VIEW 0. 0.006 0. 0.003 BOTTOM VIEW SIDE VIEW V196.15x15 package information available on Intersil’s website ISL5216 A V196.12x12 196 BALL PLASTIC BALL GRID ARRAY PACKAGE SYMBOL D/E D1/ MD/ME bbb A1 aaa CORNER NOTES: CORNER I. Controlling dimension: MILLIMETER. Converted inch B dimensions are not necessarily exact ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...