ISL5217KI Intersil, ISL5217KI Datasheet - Page 38

• Manufacturer Part Number: ISL5217KI
• Description: Up/Down Conv Mixer 2.5V 196-Pin BGA
• Manufacturer: Intersil

Specifications of ISL5217KI

• Package: 196BGA
• Maximum Power Dissipation: 1970 mW
• Operating Supply Voltage: 2.5 V

Miscellaneous Control Registers
NOTE: Test controls (10:7) are valid for Channel 0 only. They are not used and cleared to zero in channels 1-3.
14:11
14:13
BIT
BIT
14
9:8
15
12
11
10
15
10
9
7
6
5
4
3
2
1
0
8
Immediate Update (Top
Cont. Reg Update)
BIST Mode Control
Reserved
Output 2X Select
Output Mode (1:0)
FSRX and SCLKX shut off
Serial Transfer Delay
Filter Coefficient mode
Reserved
Pad hold adjustment
Pad Hold Adjustment
Pad Hold Adjustment
PN Gen Enable
PN Gen Rate
Reserved
Straight Thru
Select PN Generator
Force Edge
Force FIFO En
Force Carrier ROM
FUNCTION
FUNCTION
38
Configures output mode of device.a
Allows µP writes to bypass the update mask and load the selected top configuration slave register
immediately from the master, (requires 4 CLK synchronization). This update only affects Top Output
Routing Control, 0x79.
Built in Self Test (BIST) mode control pin. Set to 1 to enter the BIST test mode.
0=BIST Disabled (default).
1=BIST mode enabled.
Used to set the muxed I/Q at 2X rate output mode to output data at twice the sample rate. When enabled
the clock is used to select I data when the clock is high and Q data when the clock is low. This bit is only
used in conjunction with Output mode (1:0) = 01, selecting Four channel I data out at 104MHz, (4 x 20)
when disabled, and Muxed I/Q at the 2X rate when enabled.
0 = Disabled
1 = Enabled
00 = I and Q cascade in, (2 x 20), I and Q cascade out, (2 x 20)
01 = Four channel I data out at 104MHz, (4 x 20)
10 = Four channel Q data out at 104MHz, (4 x 20)
11 = Four channel muxed I/Q data out at 52MHz, (4 x 20)
Not used
FSRX and SCLKX, from default, turn off synchronously to CLK. Set to 1 to enable FSRX and SCLKX
signals to be shut off on the boundary of SCLKX.
Set both these bits to allow back-to-back serial transfers by programming the delay for the internal
serial data. Setting 0x17, bit 14 delays the internal serial data bit by the serial clock pipeline latency
through the input pad. Setting 0x17, bit 13 delays and aligns the internal sample_clk_32x to match the
FIFO timing so no dead cycles occur.
Set to 1 to enable 24-bit floating point mode. Default (reset) mode is 16-bit 2’s complement.
0=2’s complement.
1=24-bit floating point.
Not used
Hold select for serial data.
Hold select for CS and A[6:0].
Hold select for d in of IIN[19:0] and QIN[19:0].
Turn on PN Generator.
When asserted high forces PN gen to run at the clock rate. When asserted low forces PN gen to run
at the symbol rate
Not used
Pass FIFO output directly to the int filter, (bypasses the shaping filter and FM generator)
Select PN generator as the source for FIFO data in
Bypass sample NCO control and move data in the shaping and interpolation filter every clock
Bypass sample NCO control and move data from the FIFO every clock.
Force output of SIN/COS ROM, sin=cos= 0x1FFFF.
TYPE: SINGLE CHANNEL DIRECT, ADDRESS: 0x17
TYPE: DEVICE CONTROL DIRECT, ADDRESS: 0x78
.
TABLE 44. TEST CONTROL (15:0)
TABLE 45. DEVICE CONTROL
ISL5217
DESCRIPTION
DESCRIPTION
July 8, 2005
FN6004.3