ISL5217KI Intersil, ISL5217KI Datasheet
ISL5217KI
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ISL5217KI Summary of contents
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... Ordering Information PART NUMBER ISL5217KI ISL5217KIZ (Note) ISL5217EVAL1 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations ...
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Functional Block Diagram ISL5217 SERIAL SDA FM SDB INTERFACE MOD. SDC SDD I IN<15:0> Q IN<15:0> I FIFO / I IN<15:0> FIFO / Q IN<15:0> SER._PAR. MOD. TYPE <1:0> FID<31:0> SR<47:0> CHANNEL INTPL PHASES<1:0> UP PHASE OFFSET<1:0> GAIN<11:0> ...
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Pinout IOUT14 IOUT13 IOUT12 IOUT10 B IOUT16 IOUT15 IOUT11 VCCIO C IOUT18 IOUT17 QOUT16 D IOUT19 GND GND E VCCC QOUT17 QOUT18 F ISTRB VCCC QOUT19 G CLK QIN19 GND H TCK QIN17 QIN18 J IIN19 ...
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Pin Descriptions (all signals are active high unless otherwise stated) NAME TYPE POWER SUPPLY Positive Device Core Power Supply Voltage, 2.5V ±0.125V. VCCC - Positive Device Input/Output Power Supply Voltage, 3.3V ±0.165V. VCCIO - GND - Ground, 0V MICROPROCESSOR INTERFACE ...
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Pin Descriptions (all signals are active high unless otherwise stated) NAME TYPE TXENA, I Transmit Enable A-D. (TXENX) The processing channel selected for this enable will force a channel flush TXENB, (conditioned by control word 0x0c, bit 2), clear the ...
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Functional Description The ISL5217 Quad Programmable UpConverter (QPUC) converts digital baseband data into modulated or frequency translated digital samples. The QPUC can be configured to create any quadrature amplitude shift-keyed (QASK) data modulated signal, including QPSK, BPSK, and m-ary QAM. ...
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QPUC as shown in Figure 3. SCLKX MASTER µP UPDX µP FSRX ISL5217 QPUC SDX SYNCO SLAVE µP ISL5217 QPUC UPDX SLAVE µP ISL5217 QPUC UPDX SLAVE µP ISL5217 QPUC UPDX FIGURE 3. MULTIPLE CONFIGURATIONS ...
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Data Modulation Path Three data path options are provided, one for each modulation format. The modulation format is selected using FIR Control (0xd, 3:2). The modulation paths are defined in the following subsections CLK DLY DATA ...
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Modulation Mode 00 - QASK This modulation mode configures the QPUC as a BPSK, QPSK, OQPSK, MSK or m-QAM modulator. The block diagram is shown in Figure 7. The data FIFO outputs are routed to the shaping filters. Here the ...
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The maximum phase step that can occur in one clock is ±180 degrees. Table 1 provides the change in phase weighting of the input bits. TABLE 1. PHASE WEIGHTING dφ(nT)/dt 1000 0000 0000 0000 0000 0000 0000 0000 0111 ...
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Polyphase output 1 = (D1*D[n]) + (D5*D[n-1]) + (D9*D[n-2]) + (D13*D[n-3]) Polyphase output 2 = (D2*D[n]) + (D6*D[n-1]) + (D10*D[n-2]) + (D14*D[n-3]) Polyphase output 3 = (D3*D[n]) + (D7*D[n-1]) + (D11*D[n-2]) + (D15*D[n-3]) Table 4 details the coefficient address allocation ...
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Gain Control The gain control is implemented through a scaling multiplier followed by a scaling shift. The combination of the multiplier and shifter provide the final output gain of the channel. Gain adjustment can vary from -0.0026 to -144 dBFS. ...
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This would clear the NCO accumulator every 3 seconds 1/3 Hz rate. The frequency of the FID carryout can range from Fclk to Fclk/2^32. The value of FID is determined from: FID (31:0) = ...
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INTERPOLATION FILTER RESPONSE -20 -40 -60 -80 -100 -120 64 128 192 256 320 SAMPLE TIMES FIGURE 13B. INTERPOLATION FILTER IMPULSE RESPONSE L = 16; FOUT = 4096 0 -0.05 -0.1 -0.15 INTERPOLATION FILTER RESPONSE -0.2 -0.25 -0.3 -0.35 ...
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The resulting complex output is given by the following equations. Re mixer (20:0) = I(20:0) * cos(18:0) - Q(20:0) * sin(18:0) Im mixer (20:0) = Q(20:0) * cos(18:0) + I(20:0) * sin(18:0) (Vector weighting for block diagram) 1 -19 I ...
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MAIN CONTROL 0X78, BITS OUTEN 9:8 OUTPUT MODE <1:0> 01,10,11 01,10,11 01,10,11 01,10,11 4-Channel Summers Cascade Input When in the complex cascade mode the 4-channel summer re 1 and im 1 are summed with the real ...
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I/Q sample. The slave register for the I/Q samples is the first location of the FIFO. The master registers are clocked by the µP write strobe, are writable and cleared ...
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Gain Profile RAM Read/Write Procedure Write Access to the Gain Profile RAM 1. Enable the gain profile hold mode by setting bit 14 of the Main Control register 0x0c. 2. Load the RAM data to location 0x14. 3. Load the ...
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Load the RAM data to location 0x14 with the qCoef<19:4>. 4. Load the RAM data to location 0x14 with the iCoef<19:4>. 5. Load the RAM write address to location 0x15. A write strobe transfers the contents of the three ...
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Software TXENX Assertion - Upon assertion of a channel software TXENX (bit 0 of cword 0x0c), the enabled slave registers are updated. Starting Sequence Channel processing begins when the slave register of the sample frequency and the interpolation phase ...
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Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AC Electrical Specifications PARAMETER CLK Frequency CLK Clock Period CLK High CLK Low Setup Time IIN<19:0> or QIN<19:0> to CLK Hold Time IIN<19:0> or QIN<19:0> from CLK Setup Time TXENX to CLK Hold Time TXENX from CLK Setup Time UPDX ...
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AC Electrical Specifications PARAMETER IIN<19:0> or QIN<19:0> Delay Time from CLK IOUT<19:0> or QOUT<19:0> Delay Time from CLK IIN<19:0> or QIN<19:0> Valid Time from CLK, 2X Rate IOUT<19:0> or QOUT<19:0> Valid Time from CLK, 2X Rate SCLKX Valid Time from ...
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Waveforms (Continued) CLK t IQISC IN<19:0>, VALID QIN<19:0> t SDC SYNCO t IDC ISTRB t PDC VALID P<15:0> UPDX, TXENX FIGURE 21. INPUT/OUTPUT TIMING CLK IIN<19:0>, QIN<19:0>, IOUT<19:0>, QOUT<19:0> FIGURE 23. MUXED OUTPUT TIMING t RD WPWL ...
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Waveforms (Continued VALID A<6:0> t PDAC t PER P<15:0> FIGURE 27. MICROPROCESSOR READ TIMING (RDMODE = 0) Programming Information ADDRESS(6:0) (000 0000) - (001 0111) 0x00 - 0x17 (001 1000) - (001 1111) 0x18 - 0x1f (010 ...
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Device Control Registers UPDATE ADDRESS (6:0) TYPE STROBE 11 1 1000 (0x78) R 1001 (0x79) R 1010 (0x7a 1011 (0x7b 1100 (0x7c 1101 (0x7d 1110 (0x7e) ...
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BIT FUNCTION 15:2 Reserved Not Used. 1 Reset Hard Reset. Self clearing pulse zeroes data RAMs, returns master and slave configuration registers to their default values, etc. The device idle state after reset. 0 Sync Out Software ...
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BIT FUNCTION 15:0 I Channel QASK Input or I(15:0). In QASK mode, this is the I input vector. The format is 2’s complement. The MSB is bit 15. The FM Input mixer operation is: OUT = (I*COS) - (Q*SIN). In ...
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BIT FUNCTION 15:0 Carrier Phase Offset Initializes the most-significant 16-bits of the phase accumulator. The carrier phase offset is computed by the formula: Carrier Phase Offset (15:0) = INT [(Phase Offset 0 / 3600 * 2 BIT FUNCTION 15:0 Carrier ...
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TYPE: SINGLE CHANNEL DIRECT, ADDRESS: 0x0c BIT FUNCTION 15 Immediate Update 0 = Allows the configuration slave registers to be synchronously updated based the update mask Allows µP writes to bypass the update mask and load the selected ...
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BIT FUNCTION 15 Gain Profile Mode Enables gain profile to slew gain value during transitions of TX enable 14 Clear Sample Phase When enabled will clear sample phase on immediate update of sample frequency 0 = maintain sample phase 1 ...
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BIT FUNCTION 5 Sample Rate Divider 4 Sample Rate Freq 3 Sample Fine Phase 2 Sample Coarse Phase 1 Routing Control 0 I Strobe NOTES: 25. The mask register enables the slave registers to be updated from a hardware or ...
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TYPE: SINGLE CHANNEL DIRECT, ADDRESS: 0x11 BIT FUNCTION 15 Serial/parallel Data Selects the source of the symbol data for input µP port, (parallel interface) Select 1 = serial port, (one of four serial ports) 14 Epoch Frame Strobe ...
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BIT FUNCTION NOTES: 29. When in the QASK mode, the I and Q symbols will not be moved into the FIFO until both have been received. 30. When in the FM mode, the I symbol is moved to the FIFO ...
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Single Channel Indirect Registers INDIRECT ADDRESS Page Type 000 .. 07F 0 R/W 080 .. 0FF 0 100 .. 1FF 1 R/W 200 .. 2FF 2 300 .. 3FF 3 R/W 400 .. 407 4 R/W 408 .. 4FF 4-F ...
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TYPE: SINGLE CHANNEL INDIRECT, ADDRESS RANGE: 0x100-0x1ff (PAGE 1) BIT FUNCTION 15:0 Filter coefficient 256 location RAM. Use this page when the I and Q coefficients are different. NOTES: Coefficients RAM Read/Write Procedure (16-bit 2’s complement format) Write access to ...
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TYPE: SINGLE CHANNEL INDIRECT, ADDRESS RANGE: 0x300-0x3ff (PAGE 3) BIT FUNCTION 15:0 Filter coefficient 256 location RAM. Use this page when the I and Q coefficients are the same. NOTES: Coefficients RAM Read/Write Procedure (2’s complement format only) Write access ...
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Miscellaneous Control Registers BIT FUNCTION 15 FSRX and SCLKX shut off 14:13 Serial Transfer Delay 12 Filter Coefficient mode 11 Reserved 10 Pad hold adjustment 9 Pad Hold Adjustment 8 Pad Hold Adjustment 7 PN Gen Enable 6 PN Gen ...
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BIT FUNCTION 7 Sync Out Polarity Sync out polarity 0 = defines a sync assertion as a transition from a logic low to a logic high defines a sync assertion as a transition from a logic high to ...
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TYPE: DEVICE CONTROL DIRECT, ADDRESS: 0x79 BIT FUNCTION 2 Channel 0 Routing Routes channel 0 output to output summer 3 1 Channel 0 routing Routes channel 0 output to output summer 2 0 Channel 0 routing Routes channel 0 output ...
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DS[n] DS[n-1] IP0 0 16 IP1 1 17 IP2 2 18 IP3 3 19 IP4 4 20 IP5 5 21 IP6 6 22 IP7 7 23 IP8 8 24 IP9 9 25 IP10 10 26 IP11 11 27 IP12 12 ...
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Appendix A -- Errata Sheet Microprocessor Interface Issue A Chip Select (CS) operational issue has been identified and isolated to the design of the pad input circuitry in the write (WR) input cell. Under certain conditions, the combinational logic contained ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...