P87C554SBAA NXP Semiconductors, P87C554SBAA Datasheet - Page 38

• Manufacturer Part Number: P87C554SBAA
• Description: MCU 8-Bit 87C 80C51 CISC 16KB EPROM 5V 68-Pin PLCC Tube
• Manufacturer: NXP Semiconductors

Specifications of P87C554SBAA

• Package: 68PLCC
• Device Core: 80C51
• Family Name: 87C
• Maximum Speed: 16 MHz
• Ram Size: 512 Byte
• Program Memory Size: 16 KB
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Program Memory Type: EPROM
• Number Of Programmable I/os: 40
• Interface Type: I2C/UART
• On-chip Adc: 7-chx10-bit
• Operating Temperature: 0 to 70 °C
• Number Of Timers: 3

1. These frequencies exceed the upper limit of 100 kHz of the I
2. At f
Philips Semiconductors
If the STA and STO bits are both set, the a STOP condition is
transmitted to the I
mode, SIO1 generates an internal STOP condition which is not
transmitted). SIO1 then transmits a START condition.
STO = “0”: When the STO bit is reset, no STOP condition will be
generated.
SI
SI = “1”: When the SI flag is set, then, if the EA and ES1 (interrupt
enable register) bits are also set, a serial interrupt is requested. SI is
set by hardware when one of 25 of the 26 possible SIO1 states is
entered. The only state that does not cause SI to be set is state
F8H, which indicates that no relevant state information is available.
While SI is set, the low period of the serial clock on the SCL line is
stretched, and the serial transfer is suspended. A high level on the
SCL line is unaffected by the serial interrupt flag. SI must be reset
by software.
SI = “0”: When the SI flag is reset, no serial interrupt is requested,
and there is no stretching of the serial clock on the SCL line.
AA
AA = “1”: If the AA flag is set, an acknowledge (low level to SDA) will
be returned during the acknowledge clock pulse on the SCL line
when:
– The “own slave address” has been received
– The general call address has been received while the general call
– A data byte has been received while SIO1 is in the master
– A data byte has been received while SIO1 is in the addressed
AA = “0”: if the AA flag is reset, a not acknowledge (high level to
SDA) will be returned during the acknowledge clock pulse on SCL
when:
– A data has been received while SIO1 is in the master receiver
– A data byte has been received while SIO1 is in the addressed
Table 5.
NOTES:
2003 Jan 28
, THE
bit (GC) in S1ADR is set
receiver mode
slave receiver mode
mode
slave receiver mode
CR2
80C51 8-bit microcontroller – 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I
high I/O, 64L LQFP
, THE
0
0
0
0
1
1
1
1
OSC
S
A
ERIAL
SSERT
CR1
= 12 MHz/15 MHz the maximum I
0
0
1
1
0
0
1
1
I
NTERRUPT
Serial Clock Rates
A
CKNOWLEDGE
2
C bus if SIO1 is in a master mode (in a slave
CR0
0
1
0
1
0
1
0
1
F
LAG
0.24 < 62.5
F
0 < 255
3 MHz
LAG
6.25
100
23
27
31
37
50
0.49 < 62.5
2
C bus rate of 100 kHz cannot be realized due to the fixed divider rates.
0 < 254
6 MHz
BIT FREQUENCY (kHz) AT f
12.5
100
200
47
54
63
75
0.65 < 55.6
0 < 253
8 MHz
133
267
62.5
83.3
2
100
71
17
C-bus specification and cannot be used in an I
1
1
2
C, PWM, capture/compare,
38
0.98 < 50.0
The frequencies shown in Table 5 are unimportant when SIO1 is in a
slave mode. In the slave modes, SIO1 will automatically synchronize
When SIO1 is in the addressed slave transmitter mode, state C8H
will be entered after the last serial is transmitted (see Figure 43).
When SI is cleared, SIO1 leaves state C8H, enters the not
addressed slave receiver mode, and the SDA line remains at a high
level. In state C8H, the AA flag can be set again for future address
recognition.
When SIO1 is in the not addressed slave mode, its own slave
address and the general call address are ignored. Consequently, no
acknowledge is returned, and a serial interrupt is not requested.
Thus, SIO1 can be temporarily released from the I
bus status is monitored. While SIO1 is released from the bus,
START and STOP conditions are detected, and serial data is shifted
in. Address recognition can be resumed at any time by setting the
AA flag. If the AA flag is set when the part’s own slave address or
the general call address has been partly received, the address will
be recognized at the end of the byte transmission.
CR
These three bits determine the serial clock frequency when SIO1 is
in a master mode. The various serial rates are shown in Table 5.
A 12.5 kHz bit rate may be used by devices that interface to the I
bus via standard I/O port lines which are software driven and slow.
100 kHz is usually the maximum bit rate and can be derived from a
8 MHz, 6 MHz, or a 3-MHz oscillator. A variable bit rate (0.24 kHz to
62.5 kHz) may also be used if Timer 1 is not required for any other
purpose while SIO1 is in a master mode.
with any clock frequency up to 100 kHz.
The Status Register, S1STA: S1STA is an 8-bit read-only special
function register. The three least significant bits are always zero.
The five most significant bits contain the status code. There are 26
possible status codes. When S1STA contains F8H, no relevant state
information is available and no serial interrupt is requested. All other
S1STA values correspond to defined SIO1 states. When each of
these states is entered, a serial interrupt is requested (SI = “1”). A
valid status code is present in S1STA one machine cycle after SI is
set by hardware and is still present one machine cycle after SI has
been reset by software.
12 MHz
0 < 251
OSC
107
125
150
200
400
0,
94
25
CR
1
1
1
1
1
1, AND
2
1.22 < 52.1
CR
15 MHz
0 < 250
134
156
188
250
500
117
2, THE
31
1
1
1
1
1
1
2
C
LOCK
48
R
Reload value Timer 1 in Mode 2.
ATE
(256 – (reload value Timer 1))
2
C-bus application.
B
ITS
f
OSC
DIVIDED BY
80C554/87C554
128
112
96
80
48
60
30
2
C bus while the
Product data
2
C