5962-8876402LA Maxim Integrated Products, 5962-8876402LA Datasheet - Page 7

• Manufacturer Part Number: 5962-8876402LA
• Description: ADC Single Semiflash 400KSPS 8-Bit Parallel 24-Pin CDIP
• Manufacturer: Maxim Integrated Products

Specifications of 5962-8876402LA

• Package: 24CDIP
• Resolution: 8 Bit
• Sampling Rate: 400 KSPS
• Architecture: Semiflash
• Number Of Adcs: 1
• Number Of Analog Inputs: 4
• Digital Interface Type: Parallel
• Input Type: Voltage
• Polarity Of Input Voltage: Unipolar

does not require microprocessor WAIT states. A READ
operation simultaneously initiates a conversion and
reads the previous conversion result.
Figure 5 shows the timing diagram for Mode 0 opera-
tion. This is used with microprocessors that have WAIT
state capability, whereby a READ instruction is extend-
ed to accommodate slow-memory devices. Taking CS
and RD low latches the analog multiplexer address and
starts a conversion. Data outputs DB0–DB7 remain in
the high-impedance condition until the conversion is
complete.
Figure 4. Operating Sequence
Figure 5. Mode 0 Timing Diagram
RD
SETUP TIME REQUIRED
BY THE INTERNAL
COMPARATORS PRIOR TO
STARTING CONVERSION
CHANNEL
ADDRESS
ANALOG
DATA
RDY
INT
CS
RD
500ns
V
BY INTERNAL
COMPARATORS
IN
IS TRACKED
t
_______________________________________________________________________________________
1000ns
AS
t
CSS
ADDR
VALID
V
AND THE FOUR MSBs
ARE LATCHED
IN
IS SAMPLED
600ns
t
t
AH
RDY
Interface Mode 0
HIGH IMPEDANCE
CMOS, High-Speed, 8-Bit ADCs
t
CRD
INT GOING LOW
INDICATES THAT
CONVERSION IS
COMPLETE AND
THAT DATA CAN
BE READ
There are two status outputs: Interrupt (INT) and Ready
(RDY). RDY, an open-drain output (no internal pull-up
device), is connected to the processor’s READY/WAIT
input. RDY goes low on the falling edge of CS and goes
high impedance at the end of the conversion, when the
conversion result appears on the data outputs. If the RDY
output is not required, its external pull-up resistor can be
omitted. INT goes low when the conversion is complete
and returns high on the rising edge of CS or RD.
Mode 1 is designed for applications where the micro-
processor is not forced into a WAIT state. Taking CS
and RD low latches the multiplexer address and starts
a conversion (Figure 6). Data from the previous conver-
sion is immediately read from the outputs (DB0–DB7).
INT goes high at the rising edge of CS or RD and goes
low at the end of the conversion. A second READ oper-
ation is required to read the result of this conversion.
The second READ latches a new multiplexer address
and starts another conversion. A delay of 2.5µs must
be allowed between READ operations. RDY goes low
on the falling edge of CS and goes high impedance at
the rising edge of CS. If RDY is not needed, its external
pull-up resistor can be omitted.
t
ACC2
VALID
DATA
with Multiplexer
t
t
CSH
INTH
t
DH
t
P
Interface Mode 1
t
AS
t
CSS
VALID
ADDR
7