5962-8876402LA Maxim Integrated Products, 5962-8876402LA Datasheet - Page 6

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5962-8876402LA

Manufacturer Part Number
5962-8876402LA
Description
ADC Single Semiflash 400KSPS 8-Bit Parallel 24-Pin CDIP
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of 5962-8876402LA

Package
24CDIP
Resolution
8 Bit
Sampling Rate
400 KSPS
Architecture
Semiflash
Number Of Adcs
1
Number Of Analog Inputs
4
Digital Interface Type
Parallel
Input Type
Voltage
Polarity Of Input Voltage
Unipolar

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The MAX154/MAX158 and MX7824/MX7828 use what is
commonly called a “half-flash” conversion technique
(Figure 3). Two 4-bit flash ADC sections are used to
achieve an 8-bit result. Using 15 comparators, the
upper 4-bit MS (most significant) flash ADC compares
the unknown input voltage to the reference ladder and
provides the upper four data bits.
An internal DAC uses the MS bits to generate an analog
signal from the first flash conversion. A residue voltage
representing the difference between the unknown input
and the DAC voltage is then compared to the reference
ladder by 15 LS (least significant) flash comparators to
obtain the lower four output bits.
The operating sequence is shown in Figure 4. A con-
version is initiated by a falling edge of RD and CS. The
comparator inputs track the analog input voltage for
approximately 1µs. After this first cycle, the MS flash
result is latched into the output buffers and the LS con-
version begins. INT goes low approximately 600ns
later, indicating the end of the conversion, and that the
lower four bits are latched into the output buffers. The
data can then be accessed using the CS and RD
inputs.
CMOS, High-Speed, 8-Bit ADCs
with Multiplexer
Figure 3. Functional Diagram
6
_______________Detailed Description
_______________________________________________________________________________________
REF OUT**
V
V
*MAX154/MX7824 – 4-Channel Mux
** REF OUT on MAX154/MAX158 only
AIN1
AIN4
AIN8
REF
MAX158/MX7828 – 8-Channel Mux
REF
+
-
2.5V
REF
MUX*
Converter Operation
Operating Sequence
A0
ADDRESS
DECODE
LATCH
A1
A2
16
V
REF
+
The MAX154/MAX158 and MX7824/MX7828 use only
Chip Select (CS) and Read (RD) as control inputs. A
READ operation, taking CS and RD low, latches the mul-
tiplexer address inputs and starts a conversion (Table 1).
There are two interface modes, which are determined
by the length of the RD input. Mode 0, implemented by
keeping RD low until the conversion ends, is designed
for microprocessors that can be forced into a WAIT
state. In this mode, a conversion is started with a READ
operation (taking CS and RD low), and data is read
when the conversion ends. Mode 1, on the other hand,
Table 1. Truth Table for Input Channel
Selection
___________________Digital Interface
MAX154/MX7824
A1
0
0
1
1
(4MSB)
FLASH
FLASH
(4LSB)
4-BIT
4-BIT
4-BIT
ADC
DAC
ADC
RDY
A0
0
1
0
1
TIMING AND CONTROL
CIRCUITRY
A2
0
0
0
0
1
1
1
1
CS
MAX158/MX7828
A1
0
0
1
1
0
0
1
1
DRIVERS
THREE-
RD
STATE
A0
0
1
0
1
0
1
0
1
SELECTED
CHANNEL
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
INT

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