MT4LC16M4H9DJ-5 Micron Technology Inc, MT4LC16M4H9DJ-5 Datasheet - Page 4

• Manufacturer Part Number: MT4LC16M4H9DJ-5
• Description: DRAM Chip EDO 64M-Bit 16Mx4 3.3V 32-Pin SOJ Tray
• Manufacturer: Micron Technology Inc
• Type: EDOr

Specifications of MT4LC16M4H9DJ-5

• Package: 32SOJ
• Density: 64 Mb
• Address Bus Width: 12 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Random Access Time: 50 ns
• Operating Temperature: 0 to 70 °C

DRAM REFRESH (Continued)
HIGH for a minimum time of
the completion of any internal refresh cycles that may
be in process at the time of the RAS# LOW-to-HIGH
transition. If the DRAM controller uses a distributed
CBR refresh sequence, a burst refresh is not required
upon exiting self refresh. However, if the DRAM con-
troller uses RAS#-ONLY or burst CBR refresh, all rows
16 Meg x 4 EDO DRAM
D22_2.p65 – Rev. 5/00
The self refresh mode is terminated by driving RAS#
ADDR
RAS#
CAS#
ADDR
WE#
RAS#
CAS#
DQ
OE#
DQ
OE#
V
V
V
V
V
V
IOH
IOL
V
V
V
V
V
V
V
V
V
V
IOH
IOL
V
V
V
V
V
V
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
ROW
ROW
OPEN
OPEN
COLUMN (A)
COLUMN (A)
t
RPS. This delay allows for
VALID DATA (A)
The DQs go back to
Low-Z if
t OD
t OES
VALID DATA (A)
t OE
The DQs go to High-Z if WE# falls and, if
will remain High-Z until CAS# goes LOW with
WE# HIGH (i.e., until a READ cycle is initiated).
t
OES is met.
WE# Control of DQs
OE# Control of DQs
t
WHZ
VALID DATA (A)
t WPZ
COLUMN (B)
Figure 1
Figure 2
4
must be refreshed with a refresh rate of
prior to resuming normal operation.
STANDBY
memory cycle and decreases chip current to a reduced
standby level. The chip is preconditioned for the next
cycle during the RAS# HIGH time.
VALID DATA (B)
COLUMN (B)
Returning RAS# and CAS# HIGH terminates a
t
t OD
WPZ is met,
The DQs remain High-Z
until the next CAS# cycle
if
t OEHC
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
OEHC is met.
VALID DATA (B)
COLUMN (C)
WE# may be used to disable the DQs to prepare
for input data in an EARLY WRITE cycle. The DQs
will remain High-Z until CAS# goes LOW with
WE# HIGH (i.e., until a READ cycle is initiated).
t
WHZ
VALID DATA (C)
COLUMN (C)
INPUT DATA (C)
The DQs remain High-Z
until the next CAS# cycle
if
t OEP
t
OEP is met.
t OD
16 MEG x 4
EDO DRAM
COLUMN (D)
©2000, Micron Technology, Inc.
t
RC minimum
OBSOLETE
DON’T CARE
UNDEFINED
VALID DATA (D)
COLUMN (D)