MT4LC16M4H9DJ-5 Micron Technology Inc, MT4LC16M4H9DJ-5 Datasheet
MT4LC16M4H9DJ-5
Specifications of MT4LC16M4H9DJ-5
Related parts for MT4LC16M4H9DJ-5
MT4LC16M4H9DJ-5 Summary of contents
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... ** version, A12 on G3 version DJ 16 MEG x 4 EDO DRAM PART NUMBERS TG -5 PART NUMBER -6 MT4LC16M4H9DJ-x MT4LC16M4H9DJ-x S MT4LC16M4H9TG-x None MT4LC16M4H9TG MT4LC16M4G3DJ-x MT4LC16M4G3DJ-x S MT4LC16M4G3TG-x MT4LC16M4G3TG speed GENERAL DESCRIPTION The 16 Meg x 4 DRAM is a high-speed CMOS, dynamic random-access memory device containing 67,108,864 bits and designed to operate from ...
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... A5 A6 REFRESH A7 COUNTER A10 ROW- A11 ADDRESS 12 BUFFERS (12) NO. 1 CLOCK RAS# GENERATOR 16 Meg x 4 EDO DRAM D22_2.p65 – Rev. 5/00 FUNCTIONAL BLOCK DIAGRAM MT4LC16M4G3 (13 row addresses) CONTROL LOGIC 11 13 8,192 FUNCTIONAL BLOCK DIAGRAM MT4LC16M4H9 (12 row addresses) CONTROL LOGIC 12 12 4,096 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... DRAM. The refresh requirements are met by refreshing all 8,192 rows (G3) or all 4,096 rows (H9) in the DRAM array at least once every 64ms. The recommended procedure is to execute 4,096 CBR REFRESH cycles, either uniformly spaced or grouped in bursts, every 64ms ...
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... RAS# LOW-to-HIGH transition. If the DRAM controller uses a distributed CBR refresh sequence, a burst refresh is not required upon exiting self refresh. However, if the DRAM con- troller uses RAS#-ONLY or burst CBR refresh, all rows V IH ...
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... Any output at V OUT OUT DQ is disabled and in High-Z state 16 Meg x 4 EDO DRAM D22_2.p65 – Rev. 5/00 *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional ...
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... REFRESH CURRENT: Self (“S” version only) Average power supply current: CBR with t RAS# RASS (MIN) and CAS# held LOW; WE 0.2V; A0-A11, OE# and may be left open Meg x 4 EDO DRAM D22_2.p65 – Rev. 5/00 SYMBOL SPEED REFRESH REFRESH UNITS NOTES ≤ 0.2V ...
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... Output disable Output enable time OE# hold time from WE# during READ-MODIFY-WRITE cycle OE# HIGH hold time from CAS# HIGH OE# HIGH pulse width OE# LOW to CAS# HIGH setup time Output buffer turn-off delay 16 Meg x 4 EDO DRAM D22_2.p65 – Rev. 5/00 = +3.3V ±0.3V) CC SYMBOL MIN t AA ...
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... WRITE command hold time (referenced to RAS#) WE# command setup time WE# to outputs in High-Z WRITE command pulse width WE# pulse width to disable outputs WE# hold time (CBR Refresh) WE# setup time (CBR Refresh) 16 Meg x 4 EDO DRAM D22_2.p65 – Rev. 5/00 = +3.3V ±0.3V) CC SYMBOL MIN t ORD ...
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... CAC ( RAC [MIN] no longer applied). With or without the t and CAC must always be met 16. Either RCH or RRH must be satisfied for a READ cycle. 16 Meg x 4 EDO DRAM D22_2.p65 – Rev. 5/ 17. = +3.3V achieves the open circuit condition and is not CC referenced 18. operating parameters. WRITE cycles. If ...
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... CLZ 0 t CRP 5 t CSH NOTE: 1. OFF is referenced from rising edge of RAS# or CAS#, whichever occurs last. 16 Meg x 4 EDO DRAM D22_2.p65 – Rev. 5/00 READ CYCLE RAS t CSH t RSH t RCD t CAS RAD t RAH t ASC t CAH t ACH COLUMN t RCS RAC t CAC ...
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... CAH 8 t CAS 8 10,000 t CRP 5 t CSH 38 t CWL RAD 9 16 Meg x 4 EDO DRAM D22_2.p65 – Rev. 5/00 EARLY WRITE CYCLE RAS t CSH t RSH t RCD t CAS RAD t RAH t ASC t CAH COLUMN t CWL t RWL t WCR t WCS t WCH VALID DATA -6 MIN ...
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... CAS 8 10,000 t CLZ 0 t CRP 5 t CSH 38 t CWD 28 t CWL Meg x 4 EDO DRAM D22_2.p65 – Rev. 5/00 READ-WRITE CYCLE t RWC t RAS t CSH t RSH t RCD t CAS RAD t ASC t CAH t RAH COLUMN t RWD t RCS t CWD t AWD RAC t CAC t CLZ OPEN t OE ...
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... CAS 8 10,000 t CLZ 0 t COH CPA 28 t CRP 5 t CSH Meg x 4 EDO DRAM D22_2.p65 – Rev. 5/00 EDO-PAGE-MODE READ CYCLE t RASP RCD t CAS ACH t ACH t ASC t CAH t ASC COLUMN COLUMN t RCS RAC t CAC t CLZ VALID DATA OES -6 MIN MAX UNITS ...
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... ASR 0 t CAH 8 t CAS 8 10,000 CRP 5 t CSH 38 t CWL Meg x 4 EDO DRAM D22_2.p65 – Rev. 5/00 t RASP RCD t CAS ACH t ASC t CAH t ASC COLUMN COLUMN t CWL t WCH t WCS WCR VALID DATA VALID DATA -6 MIN MAX UNITS SYMBOL t ...
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... CRP 5 t CSH 38 t CWD 28 t CWL NOTE for LATE WRITE cycles only. 16 Meg x 4 EDO DRAM D22_2.p65 – Rev. 5/00 EDO-PAGE-MODE READ-WRITE CYCLE t RWC t RAS t CSH t RSH t RCD t CAS RAD t ASC t CAH t RAH COLUMN t RWD t RCS t CWD t AWD RAC t CAC ...
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... CAH 8 t CAS 8 10,000 t COH CPA 28 t CRP 5 t CSH Meg x 4 EDO DRAM D22_2.p65 – Rev. 5/00 (Pseudo READ-MODIFY-WRITE) t RASP t CSH CAS CAS ASC t CAH t ASC t CAH COLUMN (A) COLUMN (B) t RCS CPA t RAC t CAC t COH VALID DATA ( MIN MAX ...
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... ASC 0 t ASR 0 t CAC 13 t CAH 8 t CAS 8 10,000 t CLZ CRP 5 t CSH 38 16 Meg x 4 EDO DRAM D22_2.p65 – Rev. 5/00 READ CYCLE (With WE#-controlled disable) t RCD RAD t RAH t ASC ROW COLUMN t RCS OPEN -6 MIN MAX UNITS SYMBOL ...
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... CRP 5 t CSR 5 t RAH 9 NOTE: 1. End of first CBR REFRESH cycle. 16 Meg x 4 EDO DRAM D22_2.p65 – Rev. 5/00 RAS#-ONLY REFRESH CYCLE (OE# and WE# = DON’T CARE) t RAS t RAH ROW OPEN CBR REFRESH CYCLE (Addresses and OE# = DON’T CARE) t RAS ...
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... CLZ 0 t CRP NOTE HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# is LOW and OE# is HIGH. 16 Meg x 4 EDO DRAM D22_2.p65 – Rev. 5/00 HIDDEN REFRESH CYCLE (WE# = HIGH; OE# = LOW) t RAS t RCD t RSH RAD t ASC t CAH COLUMN t AA ...
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... NOTE: 1. Once RASS (MIN) is met and RAS# remains LOW, the DRAM will enter self refresh mode Once RPS is satisfied, a complete burst of all rows should be executed if RAS#-only por Burst CBR refresh is being used. 16 Meg x 4 EDO DRAM D22_2.p65 – Rev. 5/00 SELF REFRESH CYCLE (Addresses and OE# = DON’ ...
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... SEATING PLANE NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted. 2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side. 16 Meg x 4 EDO DRAM D22_2.p65 – Rev. 5/00 32-PIN PLASTIC SOJ (400 mil) .829 (21.05) ...
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... Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark of Micron Technology, Inc. 16 Meg x 4 EDO DRAM D22_2.p65 – Rev. 5/00 32-PIN PLASTIC TSOP (400 mil) SEE DETAIL A ...