PALCE16V8Z-25PI Lattice, PALCE16V8Z-25PI Datasheet - Page 27

• Manufacturer Part Number: PALCE16V8Z-25PI
• Description: SPLD PAL® Family 8 Macro Cells 50MHz EECMOS Technology 5V 20-Pin PDIP
• Manufacturer: Lattice

Specifications of PALCE16V8Z-25PI

• Package: 20PDIP
• Family Name: PAL®
• Maximum Propagation Delay Time: 25 ns
• Typical Operating Supply Voltage: 5 V
• Maximum Internal Frequency: 50 MHz
• Number Of Product Terms Per Macro: 8
• Re-programmability Support: Yes

TYPICAL I
V
The selected “typical” pattern utilized 50% of the device resources. Half of the macrocells were programmed as registered, and the
other half were programmed as combinatorial. Half of the available product terms were used for each macrocell. On any vector, half
of the outputs were switching.
By utilizing 50% of the device, a midpoint is defined for I
estimate the I
CC
= 5 V, T
150
125
100
CC
75
50
25
0
CC
A
requirements for a particular design.
0
= 25°C
CHARACTERISTICS
10
PALCE16V8 and PALCE16V8Z Families
20
I
CC
CC
. From this midpoint, a designer may scale the I
vs. Frequency
Frequency (MHz)
30
40
50
16V8H-5
16V8H-7
16V8H-10
16V8H-15/25
16V8Z-12/15
16V8Q-10/15/25
16V8Z-25
CC
graphs up or down to
16493E-9
27