H27U518S2CTP-BC HYNIX SEMICONDUCTOR, H27U518S2CTP-BC Datasheet
H27U518S2CTP-BC
Specifications of H27U518S2CTP-BC
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H27U518S2CTP-BC Summary of contents
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Mb NAND Flash This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.0 / Dec. 2008 512 ...
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Document Title 512 Mbit (64 M × 8 bit ) NAND Flash Memory Revision History Revision No. 0.0 Initial Draft 0.1 Correct Partnumber 1.0 Preliminary removed Rev 1.0 / Dec. 2008 512 Mbit ( bit) NAND Flash ...
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FEATURES SUMMARY HIGH DENSITY NAND FLASH MEMORIES - Cost effective solutions for mass storage applications NAND INTERFACE - x8 bus width - Address/ Data Multiplexing - Pinout compatiblity for all densities SUPPLY VOLTAGE - 3.3 V device : Vcc = ...
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SUMMARY DESCRIPTION Hynix NAND H27U518S2C Series have 64 M × 8 bit with spare 2 M × 8 bit capacity. The device is offered in 3.3 V Vcc Power Supply, and with x8 I/O interface. Its NAND cell provides ...
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ALE CLE IO7 - IO0 Rev 1.0 / Dec. 2008 512 Mbit ( bit) NAND Flash VCC VSS Figure 1 : Logic Diagram Data Input / Outputs CLE Command latch enable ALE Address ...
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Figure TSOP 1 Contact, x8 Device Rev 1.0 / Dec. 2008 H27U518S2C Series 512 Mbit ( bit) NAND Flash 6 ...
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Pin Description Pin Name DATA INPUTS/OUTPUTS The IO pins allow to input command, address and data and to output data during read / program IO0-IO7 operations. The inputs are latched on the rising edge of Write Enable (WE). The ...
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IO0 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle NOTE 1. L must be set to Low set to LOW or High by the Read 1 Command(00h or 01h). Density Plane Address 1 Gbit FUNCTION READ 1 ...
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CLE ALE NOTE 1. With ...
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Bus Opeation There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input, Data Output, Write Protect, and Standby. Typically glitches less than Chip Enable, Write Enable and Read ...
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DEVICE OPERATION 3.1 Page Read. Upon initial device power up, the device defaults to Read1(00h/01h) mode. This operation is also initiated by writing 00h to the command register along with followed by the four address input cycles. Once the ...
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Block Erase. The Erase operation is done on a block (16K Byte) basis. It consists of an Erase Setup command (60h), a Block address loading and an Erase Confirm Command (D0h). The Erase Confirm command (D0h) following the block ...
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Reset. The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or erase mode, the reset operation will abort these operations. The contents of ...
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OTHER FEATURES 4.1 Power Up Sequence. The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal volt- age detector disables all functions whenever Vcc is below V tection and is recommended to be kept ...
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Parameter Valid Block Number NOTE 1. The 1st block is guaranteed valid block at the time of shipment. Symbol Ambient Operating Temperature (Commercial Temperature Range Ambient Operating Temperature (Industrial Temperature Range) T Temperature Under Bias ...
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A25 ~ A0 ADDRESS REGISTER/ COUNTER PROGRAM ERASE CONTROLLER HV GENERATION ALE CLE WE CE COMMAND INTERFACE WP LOGIC RE COMMAND REGISTER DATA REGISTER Rev 1.0 / Dec. 2008 512 Mbit ( bit) NAND Flash 512 Mbit ...
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Parameter Sequential Read Operating Current Program Erase Stand-by Current (TTL) Stand-by Current (CMOS) Input Leakage Current Output Leakage Current Input High Voltage Input Low Voltage Output High Voltage Level Output Low Voltage Level Output Low Current (R/B) Vcc supply voltage ...
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Item Input / Output Capacitance Input Capacitance Table 11 : Pin Capacitance (T Parameter Program Time Number of partial Program Cycles in the same page Block Erase Time Table 12 : Program / Erase Characteristics Rev 1.0 / Dec. 2008 ...
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Parameter CLE Setup time CLE Hold time CE setup time CE hold time WE pulse width ALE setup time ALE hold time Data setup time Data hold time Write Cycle time WE High hold time Data Transfer from Cell to ...
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IO Page Program Block Erase 0 Pass / Fail Pass / Fail Ready/Busy Ready/Busy 6 Ready/Busy Ready/Busy 7 Write Protect Write Protect DEVIIDENTIFIER CYCLE 1st 2nd Part Number H27U518S2C Rev 1.0 ...
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CLE tCS CE WE ALE I/Ox Rev 1.0 / Dec. 2008 512 Mbit ( bit) NAND Flash Figure 4 : Command Latch Cycle tWC tWC tWP tWP tWH tWH tALS tALH tALS tALH tDH tDH tDS ...
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CLE CE tALS ALE WE I/Ox Notes: DIN final means 2,112Bytes (x8 I/Ox tRR R/B Figure 7 : Sequential Out Cycle after Read (CLE = ALE = L) Rev 1.0 / Dec. 2008 512 ...
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Figure 8 : Read Status Register Command Sequence and Reading Figure 9 : Read 1 Operation (Read One Page) Rev 1.0 / Dec. 2008 H27U518S2C Series 512 Mbit ( bit) NAND Flash 23 ...
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Figure 10 : Read 1 Operation Intercepted by CE CLE CE WE ALE RE I/Ox 50h Col. Add1 Row Add1 Row Add2 Col. Add R/B M Address A0-A3: Valid Address A4-A7: Dont’ care Figure 11 : Read 2 Operation (Read ...
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CLE CE tWC WE ALE RE I/Ox Col. Add1 Row Add1 Row Add2 00h Column Address Row Address R/B Note : tADL is the time from the WE# rising edge of final address cycle to the WE# rising edge fo ...
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Figure 13 : Block Erase Operation (Erase One Block) CLE CE tWC WE ALE RE I/Ox Col. Add1 Row Add1 Row Add2 00h Column Address Row Address R/B Note : tADL is the time from the WE# rising edge of ...
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CLE CE WE ALE RE 90h I/O x Read ID Command WE ALE CLE RE IO7:0 FFh R/B Rev 1.0 / Dec. 2008 512 Mbit ( bit) NAND Flash tAR tREA 00h ADh Address 1 cycle Maker ...
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Figure 17 : Power On and Data Protection Timing Rev 1.0 / Dec. 2008 H27U518S2C Series 512 Mbit ( bit) NAND Flash 28 ...
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Vcc R/B open drain output GND Device Rp value guidence Vcc (Max (min where IL is the sum of the input currents of all devices tied to the R/B pin. Rp(max) is determined ...
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Norminal Range LKO WP Figure 21 : Data Protection in relation to V NOTE : V = 1.8 V LKO Rev 1.0 / Dec. 2008 512 Mbit ( bit) NAND Flash LOCKED H27U518S2C Series ...
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Figure 20 : Pointer Operation for Programming Bad Block Management Rev 1.0 / Dec. 2008 512 Mbit ( bit) NAND Flash x8 Devices Area A Area B Area C (00h) (01h) (50h) Bytes 0-255 Bytes 256-511 Bytes ...
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Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the blocks are valid. A Bad Block does not affect the performance of valid blocks because it is isolated from ...
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Over the lifetime of the device additional Bad Blocks may develop. In this case the block has to be replaced by copying the data to a valid block. These additional Bad Blocks can be identified as attempts to program or ...
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The Erase and Program Operations are automatically reset when WP goes Low (t enabled and disabled as follows (Figure 24 ~ 27) Rev 1.0 / Dec. 2008 512 Mbit ( bit) NAND Flash Figure 24 : Enable ...
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Rev 1.0 / Dec. 2008 512 Mbit ( bit) NAND Flash Figure 26 : Enable Erasing Figure 27 : Disable Erasing H27U518S2C Series 35 ...
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Figure 28 : 48-TSOP1 - 48-lead Plastic Thin Small Outline 20mm, Package Outline Symbol alpha Table 18 : 48-TSOP1 - 48-lead Plastic Thin Small Outline, 12 × ...
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MARKING INFORMATION - ...