GAL26V12C-20LJ Lattice, GAL26V12C-20LJ Datasheet - Page 2

• Manufacturer Part Number: GAL26V12C-20LJ
• Description: SPLD - Simple Programmable Logic Devices HI PERF E2CMOS PLD
• Manufacturer: Lattice

Specifications of GAL26V12C-20LJ

• Logic Family: GAL
• Number Of Macrocells: 12
• Maximum Operating Frequency: 62.5 MHz
• Number Of Programmable I/os: 12
• Delay Time: 20 ns
• Operating Supply Voltage: 5 V
• Supply Current: 105 mA
• Maximum Operating Temperature: + 75 C
• Minimum Operating Temperature: 0 C
• Package / Case: PLCC-28
• Mounting Style: SMD/SMT
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Lead Free Status / Rohs Status: No

• HIGH PERFORMANCE E
• LOW POWER CMOS
• E
• TWELVE OUTPUT LOGIC MACROCELLS
• PRELOAD AND POWER-ON RESET OF REGISTERS
• APPLICATIONS INCLUDE:
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
The GAL26V12, at 7.5ns maximum propagation delay time, com-
bines a high performance CMOS process with Electrically Eras-
able (E
ance available of any 26V12 device on the market. E
ogy offers high speed (<100ms) erase times, providing the ability
to reprogram or reconfigure the device quickly and efficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. The GAL26V12 is fully function/fuse map/parametric
compatible with other 26V12 devices.
Unique test circuitry and reprogrammable cells allow complete
AC, DC, and functional testing during manufacture. As a result,
LATTICE is able to guarantee 100% field programmability and
functionality of all GAL
erase/rewrite cycles.
Copyright ©2000 Lattice Semiconductor Corp. GAL, E
tor Corp. The specifications herein are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 N.E. Moore Ct., Hillsboro, Oregon 97124 U.S.A.
Tel. [phone] or 1-800-LATTICE; FAX [phone]
FEATURES
— 7.5 ns Maximum Propagation Delay
— Fmax = 142.8 MHz
— 4.5 ns Maximum from Clock Input to Data Output
— TTL Compatible 16 mA Outputs
— UltraMOS
— 90 mA Typical Icc
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/Guaranteed 100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
— Maximum Flexibility for Complex Logic Designs
— 100% Functional Testability
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
DESCRIPTION
2
CELL TECHNOLOGY
2
) floating gate technology to provide the highest perform-
®
Advanced CMOS Technology
®
products. LATTICE also guarantees 100
2
CMOS
®
2
TECHNOLOGY
CMOS and UltraMOS are registered trademarks of Lattice Semiconductor Corp. Generic Array Logic is a trademark of Lattice Semiconduc-
2
technol-
INPUT/CLK 2
VCC
FUNCTIONAL BLOCK DIAGRAM
PACKAGE DIAGRAMS
I/CLK 1
I
I
I
I
I
I
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
11
5
7
9
12
4
GAL26V12
Top View
PLCC
14
2
High Performance E
16
28
18
26
25
23
21
19
I/O/Q
I/O/Q
I/O/Q
I/O/Q
GND
I/O/Q
I/O/Q
Generic Array Logic
GAL26V12
RESET
PRESET
10
12
14
16
16
14
12
10
8
8
8
8
I/CLK1
I/CLK2
OLMC 10
OLMC 11
OLMC 4
OLMC 5
OLMC 0
OLMC 3
OLMC 6
OLMC 7
OLMC 8
OLMC 9
OLMC 1
OLMC 2
Vcc
I
I
I
I
I
I
I
I
I
I
I
November 2000
1
7
14
2
26V12
CMOS PLD
GAL
DIP
28
21
15
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
INPUT
I
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
GND
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
TM