GAL26V12C-20LJ Lattice, GAL26V12C-20LJ Datasheet - Page 15

• Manufacturer Part Number: GAL26V12C-20LJ
• Description: SPLD - Simple Programmable Logic Devices HI PERF E2CMOS PLD
• Manufacturer: Lattice

Specifications of GAL26V12C-20LJ

• Logic Family: GAL
• Number Of Macrocells: 12
• Maximum Operating Frequency: 62.5 MHz
• Number Of Programmable I/os: 12
• Delay Time: 20 ns
• Operating Supply Voltage: 5 V
• Supply Current: 105 mA
• Maximum Operating Temperature: + 75 C
• Minimum Operating Temperature: 0 C
• Package / Case: PLCC-28
• Mounting Style: SMD/SMT
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Lead Free Status / Rohs Status: No

Circuitry within the GAL26V12 provides a reset signal to all reg-
isters during power-up. All internal registers will have their Q out-
puts set low after a specified time (tpr, 1μs MAX). As a result, the
state on the registered output pins (if they are enabled) will be
either high or low on power-up, depending on the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. The
timing diagram for power-up is shown below. Because of the
asynchronous nature of system power-up, some conditions must
be met to guarantee a valid power-up reset of the GAL26V12.
First, the VCC rise must be monotonic. Second, the clock input
must be at static TTL level as shown in the diagram during power
up. The registers will reset within a maximum of tpr time. As in nor-
mal system operation, avoid clocking the device until all input and
feedback path setup times have been met. The clock must also
meet the minimum pulse width requirements.
POWER-UP RESET
INPUT/OUTPUT EQUIVALENT SCHEMATICS
PIN
PIN
ESD
Protection
Circuit
ESD
Protection
Circuit
Vcc
Input
Vcc
Vcc
14
OUTPUT REGIS TER
OUTPUT REGIS TER
Q - OUTP UT
ACTIVE HIGH
ACTIV E LOW
RE GISTER
INTERNAL
Specifications GAL26V12
O u t p u t
D a t a
CLK
Vcc
O u t p u t
D a t a
F e e d b a c k
T ri - S t a t e
C o n t r o l
4.0 V
Output
V c c
t
pr
Feedback
(To Input Buffer)
Active Pull-up
Circuit
V r e f
Internal Register
Reset to Logic "0"
Device Pin
Reset to Logic "0"
Device Pin
Reset to Logic "1"
P I N
P I N