CAT24WC02J Catalyst / ON Semiconductor, CAT24WC02J Datasheet - Page 8

• Manufacturer Part Number: CAT24WC02J
• Description: EEPROM (256x8) 2k 2.5-6.0
• Manufacturer: Catalyst / ON Semiconductor

Specifications of CAT24WC02J

• Memory Size: 2 Kbit
• Organization: 256 K x 8
• Interface Type: I2C
• Maximum Clock Frequency: 0.1 MHz
• Access Time: 3500 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 3 mA
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Minimum Operating Temperature: 0 C
• Operating Supply Voltage: 2.5 V, 6 V
• Operating Temperature: 0 C to + 70 C
• Lead Free Status / Rohs Status: No

CAT24WC01/02/04/08/16
Selective Read
Selective READ operations allow the Master device to
select at random any memory location for a READ
operation. The Master device first performs a ‘dummy’
write operation by sending the START condition, slave
address and byte address of the location it wishes to
read. After the CAT24WC01/02/04/08/16 acknowledge
the word address, the Master device resends the START
condition and the slave address, this time with the R/W
bit set to one. The CAT24WC01/02/04/08/16 then
responds with its acknowledge and sends the 8-bit byte
requested. The master device does not send an
acknowledge but will generate a STOP condition.
Sequential Read
The Sequential READ operation can be initiated by
either the immediate Address READ or Selective READ
Figure 8. Immediate Address Read Timing
Doc. No. 1022, Rev. N
Not Recommended for New Design,
Replace with CAT24C01
SDA
SCL
BUS ACTIVITY:
SDA LINE
MASTER
DATA OUT
8TH BIT
8
S
S
T
A
R
T
ADDRESS
SLAVE
8
operations. After the 24WC01/02/04/08/16 sends initial
8-bit byte requested, the Master will respond with an
acknowledge which tells the device it requires more
data. The CAT24WC01/02/04/08/16 will continue to
output an 8-bit byte for each acknowledge sent by the
Master. The operation is terminated when the Master
fails to respond with an acknowledge, thus sending the
STOP condition.
The data being transmitted from the CAT24WC01/02/
04/08/16 is outputted sequentially with data from address
N followed by data from address N+1. The READ
operation address counter increments all of the
CAT24WC01/02/04/08/16 address bits so that the entire
memory array can be read during one operation. If more
than the E (where E = 255 for 24WC02, 511 for 24WC04,
1023 for 24WC08, and 2047 for 24WC16) bytes are read
out, the counter will “wrap around” and continue to clock
out data bytes. If N = E (where E = 127 for the
CAT24WC01) the counter will not 'wrap around'.
A
C
K
NO ACK
9
DATA
N
O
C
A
K
P
O
S
T
P
Characteristics subject to change without notice
STOP
© Catalyst Semiconductor, Inc.
5020 FHD F10