PCA9501D NXP Semiconductors, PCA9501D Datasheet - Page 7

• Manufacturer Part Number: PCA9501D
• Description: I/O Expanders, Repeaters & Hubs 8BIT I2C FMQB GPIONT PU2K EPR
• Manufacturer: NXP Semiconductors

Specifications of PCA9501D

• Lead Free Status / Rohs Status: Details
• Other names: PCA9501D,112

NXP Semiconductors
PCA9501_4
Product data sheet
Fig 9.
Transient pull-up current (I
SDA
IO3 output voltage
IO3 pull-up output current
SCL
7.3.1 Quasi-bidirectional I/Os
S
7.3.2 Interrupt
START condition
slave address (I/O expander)
1
0
A5 A4 A3 A2 A1 A0
2
A quasi-bidirectional I/O can be used as an input or output without the use of a control
signal for data direction. At power-on the I/Os are HIGH. In this mode, only a current
source to V
heavily loaded outputs. These devices turn on when an output is written HIGH, and are
switched off by the negative edge of SCL. The I/Os should be HIGH before being used as
inputs. See
The PCA9501 provides an open-drain output (INT) which can be fed to a corresponding
input of the microcontroller. This gives these chips a type of master function which can
initiate an action elsewhere in the system. See
An interrupt is generated by any rising or falling edge of the port inputs in the input mode.
After time t
Resetting and reactivating the interrupt circuit is achieved when data on the port is
changed to the original setting or data is read from or written to the port which has
generated the interrupt.
Resetting occurs as follows:
Each change of the I/Os after resetting will be detected and, after the next rising clock
edge, will be transmitted as INT. Reading from or writing to another device does not affect
the interrupt circuit.
3
•
•
•
•
4
In the Read mode at the acknowledge bit after the rising edge of the SCL signal
In the Write mode at the acknowledge bit after the HIGH-to-LOW transition of the SCL
signal
Returning of the port data to its original setting
Interrupts which occur during the acknowledge clock pulse may be lost (or very short)
due to the resetting of the interrupt during this pulse.
5
6
v(INT)
DD
Figure
7
OHt
R/W
is active. An additional strong pull-up to V
8
0
) while IO3 changes from LOW to HIGH and back to LOW
the signal INT is valid. See
9
A
acknowledge
from slave
9.
Rev. 04 — 10 February 2009
8-bit I
2
data to port
C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM
IO3
1
I
OHt
Figure
A
acknowledge
from slave
Figure
11.
data to port
10.
DD
IO3
0
allows fast rising edges into
I
PCA9501
A
OH
acknowledge
from slave
© NXP B.V. 2009. All rights reserved.
002aad292
P
STOP
condition
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