ispLSI2032-80LJ Lattice, ispLSI2032-80LJ Datasheet - Page 9

• Manufacturer Part Number: ispLSI2032-80LJ
• Description: CPLD - Complex Programmable Logic Devices USE ispMACH 4000V
• Manufacturer: Lattice

Specifications of ispLSI2032-80LJ

• Number Of Macrocells: 32
• Maximum Operating Frequency: 84 MHz
• Delay Time: 18.5 ns
• Number Of Programmable I/os: 32
• Operating Supply Voltage: 4.75 V to 5.25 V
• Supply Current: 40 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Package / Case: PLCC-48
• Mounting Style: SMD/SMT
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Lead Free Status / Rohs Status: No

ispLSI 2032/A Timing Model
Note: Calculations are based upon timing specifications for the ispLSI 2032/A-180L
Derivations of
GOE 0
Ded. In
Y0,1,2
I/O Pin
Reset
(Input)
t
t
t
su
h
co
2.1 ns
1.5 ns
7.7 ns
I/O Delay
#21
#20
=
=
=
=
=
=
=
=
=
=
=
=
I/O Cell
t
su,
Logic + Reg su - Clock (min)
(
(#20+ #22+ #26) + (#29) - (#20+ #22+ #35)
(0.6 + 0.7 + 4.1) + (0.5) - (0.6 + 0.7 + 2.5)
Clock (max) + Reg h - Logic
(
(#20+ #22+ #35) + (#30) - (#20+ #22+ #26)
(0.6 + 0.7 + 3.8) + (1.8) - (0.6 + 0.7 + 4.1)
Clock (max) + Reg co + Output
(
(#20+ #22+ #35) + (#31) + (#36 + #38)
(0.6 + 0.7 + 3.8) + (0.7) + (0.7 + 1.2)
t
t
t
io +
io +
io +
t
h and
t
t
t
grp +
grp +
grp +
t
t
t
co from the Product Term Clock
t
20ptxor) + (
ptck(max)) + (
ptck(max)) + (
#45
#43, 44
#42
GRP
GRP
#22
t
gsu) - (
t
t
gh) - (
gco) + (
t
Reg 4 PT Bypass
io +
t
io +
XOR Delays
#33, 34,
Control
PTs
#25, 26, 27
Feedback
t
orp +
20 PT
35
t
#24
grp +
t
grp +
Comb 4 PT Bypass #23
9
OE
RE
CK
t
ob)
t
Specifications ispLSI 2032/A
ptck(min))
t
20ptxor)
GLB
1
GLB Reg Bypass
D
RST
GLB Reg
Delay
Table 2- 0042-16/2032
#28
#29, 30,
31, 32
Q
ORP Bypass
Delay
ORP
ORP
#37
#36
#40, 41
0491/2000
#38,
39
I/O Cell
(Output)
I/O Pin