TDA18271HD/C2.557 NXP Semiconductors, TDA18271HD/C2.557 Datasheet - Page 18

• Manufacturer Part Number: TDA18271HD/C2.557
• Manufacturer: NXP Semiconductors

Specifications of TDA18271HD/C2.557

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
TDA18271HD_4
Product data sheet
9.3.10 Description of Cal post-divider byte
9.3.11 Description of Cal divider bytes 1, 2 and 3
9.3.9 Description of Easy prog byte 5
The RF tracking filters central frequency can be adjusted with the tuning word
RFC_CPROG. The RF tracking filter calibration (RFCAL) uses an internal tone at the
input of the tracking filters (generated by CAL PLL) and finds the RFC_CPROG that
corresponds to the maximum transmitted power. The RFCAL is just a small part of a more
complex algorithm fully described in the flowcharts in
The Power detection mode is a Normal mode in which the detector used for the
calibrations is switched ON. This special mode enables power sensing at the input of the
TDA18271HD and makes the power scan algorithm possible (see
“Flowchart
Table 19.
Legend: * power-on reset value.
Table 20.
Legend: * power-on reset value.
Table 21.
Legend: * power-on reset value.
Bit
7
6 to 4 IR_GSTEP[2:0]
3
2 to 0 IR_MEAS[2:0]
Bit
7 to 0
Address Register Bit
09h
0Ah
0Bh
Symbol
EXTENDED_REG
-
Symbol
CAL_POST_DIV[7:0]
CD1
CD2
CD3
EP5 - Easy prog byte 5 (subaddress 07h) bit description
CPD - Cal post-divider byte (subaddress 08h) bit description
CD1, CD2 and CD3 - Cal divider bytes 1, 2 and 3 (address 09h, 0Ah and 0Bh) bit
description
TDA18271PowerScan”).
7
6 to 0 CAL_DIV[22:16] R/W
7 to 0 CAL_DIV[15:8]
7 to 0 CAL_DIV[7:0]
Rev. 04 — 19 May 2009
Symbol
-
Access Value
R/W
R/W
R/W
R/W
Access
R/W
1
0*
011*
0*
000*
Access Value Description
R/W
R/W
R/W
Value
00h*
Description
enables extended register addressing
gain step for image rejection calibration
must be set to logic 0
image rejection measurement frequency range
(see
extended register (10h to 26h)
limited register (00h to 0Fh); only 1 byte can
be programmed after address 0Fh within 1
transmission
Table
Description
calibration synthesizer post-divider (see
Table
0*
00h*
00h*
00h*
Section
53)
48)
must be set to 0
calibration synthesizer main
divider bits
TDA18271HD
9.4.
Section 9.4.8
© NXP B.V. 2009. All rights reserved.
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