DS90C3201VS National Semiconductor, DS90C3201VS Datasheet - Page 5

• Manufacturer Part Number: DS90C3201VS
• Manufacturer: National Semiconductor

Specifications of DS90C3201VS

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / Rohs Status: Not Compliant

Symbol
LLHT
LHLT
TPPos1
TPPos0
TPPos6
TPPos5
TPPos4
TPPos3
TPPos2
TSTC
THTC
TSTC/THTC
Programmable
adjustment
TCCD
TPPLS
TPDD
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Note 5: The Minimum and Maximum Limits are based on statistical analysis of the device performance over process, voltage and temperature ranges. This
parameter is functional tested only on Automatic Test Equipment (ATE).
Note 6: Specification is guaranteed by characterization.
Note 7: A Unit Interval (UI) is defined as 1/7th of an ideal clock period (TCIP/7). E.g. For an 11.76ns clock period (85MHz), 1 UI = 1.68ns (Figure 11)
Note 8: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and LVCMOS/LVTTL I/O.
Note 9: The incremental test pattern tests device power consumption for a “typical” LCD display pattern.
Note 10: Figures 2, 4, 7 show a falling edge data strobe (TCLK IN).
Note 11: The typical transmitter TCCD latency is: 1.786*T + 4.19 ns – 2 UI, where T = TCLK IN period.
LVDS Low-to-High Transition Time (Figure 5)
LVDS High-to-Low Transition Time (Figure 5)
Transmitter Output Pulse Position for bit 1 (1st bit) (Figure 13)
Transmitter Output Pulse Position for bit 0 (2nd bit) (Figure 13)
Transmitter Output Pulse Position for bit 6 (3rd bit) (Figure 13)
Transmitter Output Pulse Position for bit 5 (4th bit) (Figure 13)
Transmitter Output Pulse Position for bit 4 (5th bit) (Figure 13)
Transmitter Output Pulse Position for bit 3 (6th bit) (Figure 13)
Transmitter Output Pulse Position for bit 2 (7th bit) (Figure 13)
Required TxIN Setup to TCLK IN (Figure 7)
Register addr 26d/19h bit [2:0] = 000b (Default)
Required TxIN Hold to TCLK IN (Figure 7)
Register addr 26d/19h bit [2:0] = 000b (Default)
Register addr 26d/19h bit [2:0] = 001b (Figure 12)
Decrease TSTC ~400ps from Default;
Increase THTC ~400ps from Default
Register addr 26d/19h bit [2:0] = 010b,
Decrease TSTC ~800ps from default;
Increase THTC ~800ps from Default
Register addr 26d/19h bit [2:0] = 011b,
Decrease TSTC ~1200ps from Default;
Increase THTC ~1200ps from Default
Register addr 26d/19h bit [2:0] = 111b,
Increase TSTC ~800ps from Default;
Decrease THTC ~800ps from Default
Register addr 26d/19h bit [2:0] = 110b,
Increase TSTC ~600ps from Default;
Decrease THTC ~600ps from Default
Register addr 26d/19h bit [2:0] = 101b,
Increase TSTC ~400ps from Default;
Decrease THTC ~400ps from Default
Register addr 26d/19h bit [2:0] = 100b,
Increase TSTC ~200ps from Default;
Decrease THTC ~200ps from Default
Transmitter TCLKIN (LVTTL) to
CLKOUT (LVDS) Latency
(Figure 7) (Note 11)
Transmitter Phase Lock Loop Set (Figure 8)
Transmitter Powerdown Delay (Figure 9)
Parameter
f = 135 MHz
f = 85 MHz (Note 6)
f = 65 MHz (Note 6)
f = 40 MHz (Note 6)
f = 25 MHz (Note 6)
f = 8 MHz
5
1 UI − 0.2
2 UI − 0.2
3 UI − 0.2
4 UI − 0.2
5 UI − 0.2
6 UI − 0.2
−0.2
Min
180
1.5
1.5
10
20
25
40
60
-0.5/
0.69
0.70
Typ
0.5/
1.5/
1.4/
1.1/
0.9/
0.6
0.6
1.0
1.5
2.0
0.3
0.5
0/
0
1
2
3
4
5
6
0
0
1 UI + 0.2 UI (Note 7)
2 UI + 0.2 UI (Note 7)
3 UI + 0.2 UI (Note 7)
4 UI + 0.2 UI (Note 7)
5 UI + 0.2 UI (Note 7)
6 UI + 0.2 UI (Note 7)
Max
+0.2
200
100
1.5
1.5
20
30
40
50
70
10
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UI (Note 7)
Units
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns