AT86RF211SAHW Atmel, AT86RF211SAHW Datasheet - Page 34

• Manufacturer Part Number: AT86RF211SAHW
• Manufacturer: Atmel

Specifications of AT86RF211SAHW

• Lead Free Status / Rohs Status: Compliant

4.6.1.2
Figure 4-29. Write Chronogram: Complete Write Cycle in a 10-bit Register
Note:
Figure 4-30. Write Chronogram: Partial Write Cycle, Writing 2 bits
34
The SCK signal must be at a logic level 0 when SLE toggles up or down.
S D A T A
0894C–WIRE–11/08
S L E
S C K
WRITE Mode (R/W = 1)
The address, R/W and data bits are clocked on the rising edge of SCK.
If the number of data bits is lower than the register capacity, the LSB bits retain their former value, allow-
ing a safe partial write. If the number of data bits is greater than the register capacity, the extra bits are
ignored.
The data is actually written into the register on the rising edge of SLE when the data length is less or
equal to the register length.
When trying to write more data than the register length, a data field is written on the first extra rising clock
edge of the register length.
The complete 10-bit register is updated on a rising edge of SLE.
Only the 2 MSBs are updated on the rising edge of SLE; other register bits remain unchanged.
A[3]
S L E
S C K
S D A T A
A[2]
A[1]
A[0]
A[3]
R / W
A[2]
D[9]
A[1]
D[8]
A[0]
D[7]
R / W
D[6]
D[31]
D[5]
D[30]
D[4]
D[3]
D[2]
D[1]
e2v semiconductors SAS 2008
D[0]
AT86RF211S