AT86RF211SAHW Atmel, AT86RF211SAHW Datasheet - Page 30

• Manufacturer Part Number: AT86RF211SAHW
• Manufacturer: Atmel

Specifications of AT86RF211SAHW

• Lead Free Status / Rohs Status: Compliant

4.4.5
Figure 4-28. Benefits of Resynchronization
30
0894C–WIRE–11/08
Data Resynchronization
DATAMSG
DATACLK
Figure 4-27. Clock Recovery Target Position
Note:
As the AT86RF211S can provide a synchronization signal together with the demodulated data on pins
DATAMSG and DATACLK, it is also possible to reshape the data received.
In resynchronization mode the signals provided to the companion MCU are filtered; the jitter of the gen-
erated clock remains the only concern. The bit decision is then fully performed on the chip, thus
removing real-time constraints on the MCU. This facilitates the data transfer, independently of the cho-
sen protocol (UART, USART, SPI etc.)
Note:
Figure 4-28
clock centered on the half bit.
Center of
Use the above settings to ensure a good trade-off between the settling time and the jitter of the clock. The
clock remains correct, regardless of the number of transitions in the received stream, as long as the refer-
ence clocks of Tx and Rx are the same. Example: if D (Rx - Tx) = 20 ppm, the clock is centered at ±20% for
at least 0.2/20.10
Resynchronizations add a short latency time on the data; this does not affect transmission.
Case No. 1: no resynchronization
bit
shows that the data provided to the MCU has a perfect bit period, with the synchronization
First random position of
clock's rising edge
DATAMSG
DATACLK
median
Clock
time
uncertainty
-6
= 10 Kbits.
Clock
Target position of
clock's rising edge
reception quality
depending on
Data jitter
1 x Tol
Case No. 2: resynchronization
Uncertainty area
+/- 10%
50%
Center of bit
+/- Tol = uncertainty
50%
e2v semiconductors SAS 2008
AT86RF211S