ATA5824-PLQW 80 Atmel, ATA5824-PLQW 80 Datasheet - Page 29
![](/photos/40/57/405769/48pin_qfn_sml.jpg)
ATA5824-PLQW 80
Manufacturer Part Number
ATA5824-PLQW 80
Description
Manufacturer
Atmel
Datasheet
1.ATA5824-PLQW_80.pdf
(98 pages)
Specifications of ATA5824-PLQW 80
Operating Temperature (min)
-40C
Operating Temperature (max)
105C
Operating Temperature Classification
Industrial
Product Depth (mm)
7mm
Product Height (mm)
0.9mm
Product Length (mm)
7mm
Operating Supply Voltage (typ)
5V
Lead Free Status / Rohs Status
Compliant
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4829D–RKE–06/06
To save current in IDLE and Sleep mode, the load capacitors partially are switched off in this
modes with S
It is recommended to use a crystal with C
C
Lower values of C
higher values of C
Figure 9-2.
To find the right values used in the control registers 2 and 3 (see
Table 12-10 on page
determine the right content, the frequency at pin CLK, as well as the output frequency at
RF_OUT in ASK mode can be measured, than the FREQ value can be calculated according to
Table 9-1
0
= 1.0 pF to 2.2 pF.
In IDLE mode and during Sleep mode (RX_Polling)
8 pF
S1
so that f
XTAL1
the switches S1 and S2 are open.
10 pF
1
XTO Block Diagram
and S
m
m
RF
C
L1
can be used, this increases slightly the start-up time. Lower values of C
(up to 15 fF) can also be used, this has only little influence to pulling.
is exactly the desired radio frequency.
2
39) the relationship between f
seen in
XTAL2
C
L2
Figure 9-2 on page
10 pF
8 pF
S2
f
XTO
m
= 3.0 fF to 7.0 fF, C
Baud1
29.
Amplitude
detector
Divider
Divider
Divider
XTO
Baud0
/16
/16
/3
/1
/2
/4
/8
and the f
XLim
ATA5823/ATA5824
CLK_EN
(control
register 3)
RF
CLK
Table 12-7 on page 38
LN
is shown in
f
f
DCLK
XDCLK
&
= 9 pF, R
CLK_ON
(control
register 3)
(to reset logic)
XTO_OK
DVCC_OK
(from power supply)
m
Table
< 120
9-1. To
and
and
0
29
or
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