ST70137 STMicroelectronics, ST70137 Datasheet - Page 13

• Manufacturer Part Number: ST70137
• Manufacturer: STMicroelectronics

Specifications of ST70137

• Screening Level: Commercial
• Lead Free Status / Rohs Status: Not Compliant

ST70137
PIN DESCRIPTION (continued)
TEST CONDITION
All Ouputs have been loaded with.
* See text scheme at page 20.
13/22
CFG_MEM INTERFACE
CFG_SCE
CFG_SCK/GPO[ 6]
CFG_SDI
CFG_SDO/GPO[ 7]
JTAG INTERFACE
TDI
TDO
TMS
TCK
TRSTB
Signal Name
Outputs
Others
USB *
PCI
Direction Init Status
O
O
O
O
I
I
I
I
I
IH
IH
IL
IL
L
L
L
Minimum
-
I
0
0
0
Polarity
H
H
L
L
-
-
-
-
-
Chip Enable
This pin is designed to directly interface to a serial
EEPROM that use the 93C66 EEPROM interface proto-
col. This pin has to be connected directly to the
EEPROM’s chip select pin.
Serial Clock or General Purpose Output Pin 6 depending
on the internal selection. The selection is performed writ-
ing the proper bit inside the PCFW or UCFW register. At
the power-on or hardware reset the CFG_CLK functional-
ity is selected. This pin is designed to directly interface to
a serial EEPROM that use the 93C66 EEPROM interface
protocol.
Serial Data Input
Data going into this pin has to be generated on the rising
edge of CFG_SCK. This pin is designed to directly inter-
face to a serial EEPROM that use the 93C66 EEPROM
interface protocol.
Serial Data/Address Output
General Purpose Output Pin 7 depending on the internal
selection. The selection is performed writing the proper bit
inside the PCFW or UCFW register. At the power-up or
hardware reset the CFG_SDO functionality is selected.
The CFG_SDO data change is synchronous with the fall-
ing edge of CFG_SCK. This pin is designed to directly
interface to a serial EEPROM that use the 93C66
EEPROM interface protocol.
JTAG Test Data Input.
JTAG Test Data Output.
JTAG Test Mode Select.
JTAG Test Clock.
JTAG Reset (active Low).
Maximum
50
50
15
Signal Description
Unit
pF
pF
pF