TXC-04251AIPQ Transwitch Corporation, TXC-04251AIPQ Datasheet - Page 15

• Manufacturer Part Number: TXC-04251AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-04251AIPQ

• Pin Count: 160
• Screening Level: Industrial
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

MICROPROCESSOR BUS INTERFACE
UPAD(7-0)
Symbol
QUIETn
Symbol
INT/INT
(n=1-4)
(n=1-4)
TLOSn
INTSH
TNIn/
SEL
ALE
WR
RD
133, 132,
130, 129,
128, 126,
125, 124
Pin No.
20, 105,
18, 107,
Pin No.
7, 117
5, 119
146
147
148
149
152
150
I/O/P
I/O/P
O(T)
I/O
I
I
I
I
I
I
I
TTLs
TTLs
TTLs
TTLs
Type
Type
8mA
8mA
TTL
TTL
TTL
TTL
TTL
DATA SHEET
Transmit Port n Data Negative Rail/External Loss Of
Signal: When control bit BYPASn is 0, negative rail input
data is provided on this pin. When control bit BYPASn is 1,
this pin may be used to input an active low external loss of
signal indicator from the line interface device.
Quiet Port n: A high forces the RPOn and RNOn pins to
the 0 state for either a rail or NRZ interface, overriding
control bit RnEN. A low allows the state of the RPOn and
RNOn pins to be controlled by RnEN.
Address/Data Bus: These pins constitute the time-
multiplexed address and data bus for accessing the
registers which reside in the memory map of the Quad T1
Mapper. UPAD7 is the most significant bit. High is logic 1.
Select: A low signal generated by the microprocessor for
accessing the memory map registers for control, status,
and alarm information.
Read: A low signal generated by the microprocessor for
reading the registers which reside in the memory map.
The memory map is selected by placing a low on the
select pin.
Write: A low signal generated by the microprocessor for
writing to the registers which reside in the memory map.
The memory map is selected by placing a low on the
select pin.
Address Latch Enable: An active high signal generated
by the microprocessor for holding an address stable
during a read/write cycle.
Interrupt: A high or low on this output pin signals an
interrupt request to the microprocessor. The polarity of
this signal is determined by the state of the INTSH pin.
Interrupt Sense High Selection: A high on this pin
causes the interrupt sense to be high when an interrupt
occurs. A low causes the interrupt sense to be low when
an interrupt occurs.
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Name/Function
Name/Function
Ed. 4, March 2000
TXC-04251
TXC-04251-MB
QT1M