W91031S Winbond Electronics, W91031S Datasheet - Page 12

• Manufacturer Part Number: W91031S
• Manufacturer: Winbond Electronics

Specifications of W91031S

• Process Technology: CMOS
• Operating Frequency (max): 3580kHz
• Mounting: Surface Mount
• Supply Current: 2.5mA
• Lead Free Status / Rohs Status: Not Compliant

Other Functions
Interrupt
The interrupt INTN is an open drain output and is used to interrupt the microcontroller. Either RNGON
low, FDRN low or ALGO high will set INTN low and will remain low until all of these three pins return
to an inactive state. The microcontroller must read these pins to know what kind of interrupt occurred
and to make the correct interrupt response.
When the system is powered on, there is no charge on the capacitors. The voltage on the RNGRC pin
is low and RNGON will be low. Also the voltage on the ALGRC pin is high and ALGO will be high if
the SLEEP pin is low. This will cause an interrupt upon power up which will not be cleared until both
capacitors are charged. The microcontroller should therefore ignore the interrupt from these source
until the capacitors are charged up. The microcontroller can examine the RNGON and ALGO pins
and wait until these signals are inactive during a power on interrupt.
It is possible to clear the ALGO pin and its interrupt quickly by setting the SLEEP pin high. In the
sleep mode, the ALGO pin is forced low and the charge switch in Figure 7-4 will turn on, forcing the
capacitor to charge up rapidly.
Sleep Mode
The W91031 can go into a sleep mode by setting SLEEP high, resulting in reduced power
consumption. In this mode, the gain control op-amp, oscillator and all internal circuits, except the ring
detector are disabled. The RNGDI, RNGRC and RNGON pins are not affected, so the device can still
react to call arrival indicators and activate an interrupt to wake up the microcontroller. The sleep
mode can be disabled by the microcontroller.
Notes:
1. FDRN cleared to high by DCLK.
2. FDRN not cleared, low for maximum time (1/2 bit width).
Demodulated
bit stream
internal
DCLK
DATA
FDRN
(N - 1)th byte data
Nth byte data
b6
b5
Figure 7-8. Serial Data Interface Timing of FSK Demodulation in Mode 1
b6
b7
b7
stop
1
Note 1
b0 b1 b2 b3 b4 b5 b6 b7
t
DDS
t
DDH
start
0
b0
b1
- 12 -
b2
1/f
(N + 1)th byte data
DCLK1
b3
Nth byte data
b4
Preliminary W91031
b5
b6
b7
stop start
1
Note 2
t
RL
0
b0
b0