W91031S Winbond Electronics, W91031S Datasheet - Page 10

• Manufacturer Part Number: W91031S
• Manufacturer: Winbond Electronics

Specifications of W91031S

• Process Technology: CMOS
• Operating Frequency (max): 3580kHz
• Mounting: Surface Mount
• Supply Current: 2.5mA
• Lead Free Status / Rohs Status: Not Compliant

FSK Demodulation
The FSK demodulation circuit is enabled when the FSKE signal is high. An enable time is required to
enable the FSK demodulator circuitry after the FSKE signal goes from low to high.
FSK Carrier Detector
The FSK carrier detector provides an indication of the presence of a signal within the FSK frequency
band. If the output amplitude of the FSK bandpass filter is of sufficient magnitude and holds for 8 mS,
the FSK carrier detect output signal FCDN goes low. FCDN will be released if the FSK bandpass filter
output amplitude is of insufficient magnitude for greater than 8 mS. The 8 mS hysteresis of the FSK
carrier detector is to allow for momentary signal drop out after FCDN has been activated.
When FCDN is inactive, the output of the FSK demodulator is ignored by the FSK data output
interface. In mode 0 of the 3-wire FSK data output interface, DCLK DATA and FDRN are all high and
no clock and no data is driven. In mode 1, the internal shift registers are not updated, and FDRN is
inactive (high state). The DATA is undefined if DCLK is clocked.
3-wire FSK Interface
The 3-wire interface, DCLK, DATA and FDRN pins, form the data interface of the FSK demodulation.
The DCLK pin is the data clock which is either generated by the W91031 or by an external device.
The DATA pin is the serial data pin that outputs data to external devices. The FDRN pin is the data
ready signal, also an output from the W91031 to external devices. There are two modes of this 3-wire
interface that can be selected. Mode 0, where the data transfer is initiated by the W91031 device, or
Mode 1, where the data transfer is initiated by an external microcontroller.
(a) t
t
t
R
V
GP
GA
D
P
= R
= R1 R2 / (R1 + R2)
= diode forward voltage
= R1 C ln [V
GP
W91031
P
> t
C ln [(V
GA
DD
DD
/ (V
-V
Figure 7-6. Guard Time Circuits with Unequal Present and Absent Time
D
DD
(R
-V
P
/ R2)) / (V
CPth
V
ALGRC
ALR
DD
)]
CPth
R1
-V
C
D
(R
R2
P
/ R2))]
- 10 -
(b) t
t
t
R
V
GA
GP
D
P
= diode forward voltage
= R
= R1 C ln [V
= R1 R2 / (R1 + R2)
W91031
GP
P
> t
C ln [(V
GA
DD
DD
-V
/ (V
D
Preliminary W91031
DD
(R
- V
P
ALGRC
ALR
/ R2)) / (V -V
V
CPth
DD
)]
R1
DD
C
CPth
R2
-V
D
(R
P
/ R2))]