TE28F160S570 Intel, TE28F160S570 Datasheet - Page 28

• Manufacturer Part Number: TE28F160S570
• Manufacturer: Intel

Specifications of TE28F160S570

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 21/20Bit
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 4.5 to 5.5V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8/16Bit
• Number Of Words: 2M/1M
• Supply Current: 65mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

28F160S5/28F320S5
suspended. The only other valid commands while
programming is suspended are Read Status
Register and Program Resume. After a Program
Resume command is written, the WSM will
continue the programming process. Status register
bits SR.2 and SR.7 will automatically clear and STS
in RY/BY# mode will return to V
Program Resume command is written, the device
automatically outputs status register data when
read. V
remain at V
for programming) while in program suspend mode.
RP# must also remain at V
used for programming). Refer to Figure 8 for the
Program Suspend/Resume Flowchart .
4.13
A flexible block locking and unlocking scheme is
enabled via a combination of block lock-bits. The
block lock-bits gate program and erase operations.
With WP# = V
set using the Set Block Lock-Bit command.
Set block lock-bit is initiated using a two-cycle
command sequence. The Set Block Lock-Bit setup
along with appropriate block or device address is
written followed by the Set Block Lock-Bit Confirm
and an address within the block to be locked. The
WSM then controls the set lock-bit algorithm. After
the sequence is written, the device automatically
outputs status register data when read. The CPU
can detect the completion of the set lock-bit event
by analyzing STS in level RY/BY# mode or status
register bit SR.7.
When the set lock-bit operation is complete, status
register bit SR.4 should be checked. If an error is
detected, the status register should be cleared. The
CUI will remain in read status register mode until a
new command is issued.
This two-step sequence of setup followed by
execution ensures that lock-bits are not accidentally
set. An invalid Set Block Lock-Bit command will
result in status register bits SR.4 and SR.5 being
set to “1.” Also, reliable operations occur only when
V
voltages, lock-bit contents are protected against
alteration.
28
CC
= V
PP
CC1/2
Set Block Lock-Bit Command
CC1/2
must remain at V
and V
IH
(the same V
, individual block lock-bits can be
PP
= V
PPH
IH
PP
. In the absence these
(the same RP# level
PPH
and V
and V
CC
OL
. After the
levels used
CC
must
A successful set block lock-bit operation requires
that WP# = V
the operation will fail and SR.1 and SR.4 will be set
to “1.” See Table 13 for write protection alternatives.
Refer to Figure 11 for the Set Block Lock-Bit
Flowchart .
4.14
All set block lock-bits are cleared in parallel via the
Clear Block Lock-Bits command. This command is
valid only when WP# = V
The clear block lock-bits operation is initiated using
a two-cycle command sequence. A Clear Block
Lock-Bits setup command is written followed by a
Confirm command. Then, the device automatically
outputs status register data when read (see Figure
12). The CPU can detect completion of the clear
block lock-bits event by analyzing STS in level
RY/BY# mode or status register bit SR.7.
This two-step sequence of set-up followed by
execution ensures that block lock-bits are not
accidentally
Lock-Bits command sequence will result in status
register bits SR.4 and SR.5 being set to “1.” Also, a
reliable clear block lock-bits operation can only
occur when V
block lock-bits operation is attempted while V
V
absence of these voltages, the block lock-bits
contents
successful clear block lock-bits operation requires
that WP# = V
If a clear block lock-bits operation is aborted due to
V
WP# active transition, block lock-bit values are left
in an undetermined state. A repeat of clear block
lock-bits is required to initialize block lock-bit
contents to known values.
When the operation is complete, status register bit
SR.5 should be checked. If a clear block lock-bit
error is detected, the status register should be
cleared. The CUI will remain in read status register
mode until another command is issued.
PPLK
PP
or V
, SR.3 and SR.5 will be set to “1.” In the
CC
Clear Block Lock-Bits
Command
are
transitioning out of valid range or RP# or
IH
CC
IH
cleared.
.
. If it is attempted with WP# = V
protected
= V
CC1/2
An
IH
and V
PRELIMINARY
.
against
invalid
PP
= V
alteration.
PPH
Clear
. If a clear
Block
PP
IL
A
,