TE28F160S570 Intel, TE28F160S570 Datasheet - Page 15

• Manufacturer Part Number: TE28F160S570
• Manufacturer: Intel

Specifications of TE28F160S570

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 21/20Bit
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 4.5 to 5.5V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8/16Bit
• Number Of Words: 2M/1M
• Supply Current: 65mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

NOTES:
1. Bus operations are defined in Table 2.
2. X = Any valid address within the device.
3. ID = Data read from Identifier Codes.
4. The upper byte of the data bus (DQ
5. Following the Read Identifier Codes command, read operations access manufacturer, device, and block-lock codes. See
6. If a block is locked (i.e., the block’s lock-bit is set to 0), WP# must be at V
7. Either 40H or 10H are recognized by the WSM as the byte/word program setup.
8. After the Write to Buffer command is issued, check the XSR to make sure a Write Buffer is available.
9. N = byte/word count argument such that the number of bytes/words to be written to the input buffer = N + 1. N = 0 is 1
10. The write to buffer, block erase, or full chip erase operation does not begin until a Confirm command (D0h) is issued.
11. A block lock-bit can be set only while WP# is V
12. WP# must be at V
13. Commands other than those shown above are reserved for future use and should not be used.
14. The Basic Command Set (BCS) is the same as the 28F008SA Command Set or Intel Standard Command Set. The
PRELIMINARY
BA = Address within the block being erased or locked.
IA = Identifier Code Address: see Table 12.
QA = Query database Address.
PA = Address of memory location to be programmed.
QD = Data read from Query database.
SRD = Data read from status register. See Table 15 for a description of the status register bits.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE#.
CC = Configuration Code. (See Table 14.)
Section 4.3 for read identifier code data.
suspend operations. Attempts to issue a block erase, program and suspend operation to a locked block while WP# is V
will fail.
byte/word length, and so on. Write to Buffer is a multi-cycle operation, where a byte/word count of N + 1 is written to the
correct memory address (WA) with the proper data (WD). The Confirm command (D0h) is expected after exactly N + 1 write
cycles; any other command at that point in the sequence aborts the buffered write. Writing a byte/word count outside the
buffer boundary causes unexpected results and should be avoided.
Confirm also reactivates suspended operations.
Scaleable Command Set (SCS) is also referred to as the Intel Extended Command Set.
IH
to clear block lock-bits. The clear block lock-bits operation simultaneously clears all block lock-bits.
8–15
) during command writes is a “Don’t Care” in x16 operation.
IH
.
IH
in order to perform block erase, program and
28F160S5/28F320S5
IL
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