ELANSC400-66AI AMD (ADVANCED MICRO DEVICES), ELANSC400-66AI Datasheet - Page 105

• Manufacturer Part Number: ELANSC400-66AI
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ELANSC400-66AI

• Cpu Family: Elan
• Device Core Size: 16/32Bit
• Frequency (max): 66MHz
• Interface Type: ISA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 95C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 292
• Package Type: BGA
• Lead Free Status / Rohs Status: Not Compliant

Symbol
t13a
t13b
t22a
t22b
t11a
t11b
t13c
t1a
t1b
t2a
t2b
t3a
t3b
t3d
t3e
t3g
t3h
t5a
t5b
t7a
t7b
t12
t14
t15
t16
t17
t19
t20
t21
t23
t24
t25
t26
t27
t3c
t3f
t4
t6
t8
t9
Parameter Description
Setup, SA, SBHE stable to command assertion, 16-bit I/O,
8-bit I/O, Mem
Setup, SA, SBHE stable to command assertion, 16-bit Mem
Delay, MCS16 stable from SA
Delay, IOCS16 stable from SA
Pulse width, IOW, 8-bit cycle
Pulse width, MEMW, 8-bit cycle
Pulse width, IOR, 8-bit cycle
Pulse width, MEMR, 8-bit cycle
Pulse width, IOW, 16-bit cycle
Pulse width, IOR, 16-bit cycle
Pulse width, MEMR, 16-bit cycle
SA, SBHE hold from command deassertion
IOCHRDY delay from IOR, MEMR, IOW, MEMW (8-bit)
IOCHRDY delay from IOR, MEMR, IOW, MEMW (16-bit)
IOR, MEMR, IOW, MEMW delay from IOCHRDY
IOR, MEMR, IOW, MEMW high time (8-bit)
IOR, MEMR, IOW, MEMW high time (16-bit)
Delay, BALE rising from IOR, MEMR, IOW, MEMW deassertion
IOCHRDY pulse width
Setup, SD to write command assertion, 8-bit memory, I/O write and
16-bit I/O write
Setup, SD to write command assertion, 16-bit memory write
Hold, SD from write command deassertion
Data access time, 8-bit read
Data access time, 16-bit I/O read
Data access time, 16-bit memory read
Hold, SD from read command deassertion
Setup, SA, SBHE stable to BALE falling edge
Pulse width, BALE
Setup, AEN high to IOR/IOW assertion
Setup, SA, SBHE stable to command assertion
Hold, DRQ from DACK assertion
Setup, DACK assertion to I/O command assertion
Setup, IOR assertion to MEMW command
Setup, MEMR command assertion to IOW command
Delay, IOCHRDY assertion to command high
Delay, memory command to IOCHRDY deassertion
Hold, command off to DACK off
Hold, read command off from write command off
Hold, AEN from command off
Pulse width, MEMW, 16-bit cycle
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
Table 38. ISA Cycles
Notes
120 ns 15.6 s
External Bus
Min
240
120
120
530
530
530
530
165
165
240
125
187
125
145
102
145
235
200
-29
30
50
60
53
46
33
61
60
60
0
0
0
33-MHz
Max
489
132
102
122
378
209
125
66
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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