PI7C8150BND Pericom Semiconductor, PI7C8150BND Datasheet - Page 5

• Manufacturer Part Number: PI7C8150BND
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150BND

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

5
6
7
8
9
10
11
12
4.3
4.4
5.1
5.2
5.3
5.4
6.1
6.2
6.3
6.4
7.1
7.2
7.3
8.1
8.2
9.1
9.2
10.1
10.2
10.3
12.1
12.2
12.3
4.3.1
4.3.2
4.4.1
4.4.2
TRANSACTION ORDERING.......................................................................................................... 35
ERROR HANDLING......................................................................................................................... 38
6.2.1
6.2.2
6.2.3
6.2.4
EXCLUSIVE ACCESS ...................................................................................................................... 49
7.2.1
7.2.2
PCI BUS ARBITRATION................................................................................................................. 51
8.2.1
8.2.2
8.2.3
8.2.4
CLOCKS ............................................................................................................................................. 55
GENERAL PURPOSE I/O INTERFACE.................................................................................... 55
PCI POWER MANAGEMENT .................................................................................................... 58
RESET............................................................................................................................................. 59
MEMORY ADDRESS DECODING............................................................................................ 31
VGA SUPPORT ........................................................................................................................... 34
TRANSACTIONS GOVERNED BY ORDERING RULES ........................................................ 35
GENERAL ORDERING GUIDELINES...................................................................................... 36
ORDERING RULES .................................................................................................................... 36
DATA SYNCHRONIZATION .................................................................................................... 37
ADDRESS PARITY ERRORS .................................................................................................... 38
DATA PARITY ERRORS............................................................................................................ 39
DATA PARITY ERROR REPORTING SUMMARY ................................................................. 44
SYSTEM ERROR (SERR#) REPORTING.................................................................................. 48
CONCURRENT LOCKS ............................................................................................................. 49
ACQUIRING EXCLUSIVE ACCESS ACROSS PI7C8150........................................................ 49
ENDING EXCLUSIVE ACCESS ................................................................................................ 51
PRIMARY PCI BUS ARBITRATION......................................................................................... 52
SECONDARY PCI BUS ARBITRATION .................................................................................. 52
PRIMARY CLOCK INPUTS....................................................................................................... 55
SECONDARY CLOCK OUTPUTS............................................................................................. 55
GPIO CONTROL REGISTERS ................................................................................................... 55
SECONDARY CLOCK CONTROL............................................................................................ 56
LIVE INSERTION ....................................................................................................................... 58
PRIMARY INTERFACE RESET ................................................................................................ 59
SECONDARY INTERFACE RESET .......................................................................................... 59
CHIP RESET ................................................................................................................................ 60
MEMORY-MAPPED I/O BASE AND LIMIT ADDRESS REGISTERS ......................... 32
PREFETCHABLE MEMORY BASE AND LIMIT ADDRESS REGISTERS ................. 33
VGA MODE......................................................................................................................... 34
VGA SNOOP MODE........................................................................................................... 34
CONFIGURATION WRITE TRANSACTIONS TO CONFIGURATION SPACE.......... 39
READ TRANSACTIONS .................................................................................................... 39
DELAYED WRITE TRANSACTIONS............................................................................... 40
POSTED WRITE TRANSACTIONS.................................................................................. 43
LOCKED TRANSACTIONS IN DOWNSTREAM DIRECTION ..................................... 49
LOCKED TRANSACTION IN UPSTREAM DIRECTION .............................................. 51
SECONDARY BUS ARBITRATION USING THE INTERNAL ARBITER.................... 52
PREEMPTION .................................................................................................................... 54
SECONDARY BUS ARBITRATION USING AN EXTERNAL ARBITER...................... 54
BUS PARKING.................................................................................................................... 54
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March 19, 2003 – Revision 1.04
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
PI7C8150