DSPB56364FU100 Freescale Semiconductor, DSPB56364FU100 Datasheet - Page 9

• Manufacturer Part Number: DSPB56364FU100
• Manufacturer: Freescale Semiconductor

Specifications of DSPB56364FU100

• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 9KB
• Program Memory Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.14V
• Operating Supply Voltage (max): 3.46V
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• Lead Free Status / Rohs Status: Not Compliant

2.5.2
2.5.3
Freescale Semiconductor
RAS0
Signal Name
Signal
D0–D7
Name
AA0–AA1/
CAS
WR
RD
TA
–
RAS1
External Data Bus
External Bus Control
Output
Input/
Type
Output
Output
Output
Output
Type
Input
State During
Tri-stated
State During
Ignored Input Transfer Acknowledge—If there is no external bus activity, the
Reset
Tri-stated
Tri-stated
Tri-stated
Tri-stated
Reset
Table 2-7 External Bus Control Signals
Data Bus—D0–D7 are active-high, bidirectional input/outputs that provide the
bidirectional data bus for external program and data memory accesses. D0–D7 are
tri-stated during hardware reset and when the DSP is in the stop or wait low-power
standby mode.
Table 2-6 External Data Bus Signals
Address Attribute or Row Address Strobe—When defined as AA, these signals
can be used as chip selects or additional address lines. When defined as
these signals can be used as
tri-stateable outputs with programmable polarity. These signals are tri-stated during
hardware reset and when the DSP is in the stop or wait low-power standby mode.
Column Address Strobe—
the column address. This signal is tri-stated during hardware reset and when the
DSP is in the stop or wait low-power standby mode.
Read Enable—
on the data bus. This signal is tri-stated during hardware reset and when the DSP
is in the stop or wait low-power standby mode.
Write Enable—
memory on the data bus. This signal is tri-stated during hardware reset and when
the DSP is in the stop or wait low-power standby mode.
The
external bus cycle indefinitely. Any number of wait states (1, 2. . .infinity) may be
added to the wait states inserted by the BCR by keeping
operation,
completion of the bus cycle, and is deasserted before the next bus cycle. The
current bus cycle completes one clock period after
the internal system clock. The number of wait states is determined by the
or by the bus control register (BCR), whichever is longer. The BCR can be used to
set the minimum number of wait states in external bus cycles.
In order to use the TA functionality, the BCR must be programmed to at least one
wait state. A zero wait state access cannot be extended by TA deassertion,
otherwise improper operation may result.
asynchronously, depending on the setting of the TAS bit in the operating mode
register (OMR).
TA
improper operation may result.
DSP56364 Technical Data, Rev. 4.1
functionality may not be used while performing DRAM type accesses, otherwise
TA
input is a data transfer acknowledge (DTACK) function that can extend an
TA
is deasserted at the start of a bus cycle, is asserted to enable
RD
WR
is an active-low output that is asserted to read external memory
is an active-low output that is asserted to write external
CAS
Signal Description
RAS
Signal Description
is an active-low output used by DRAM to strobe
for DRAM interface. These signals are
External Memory Expansion Port (Port A)
TA
can operate synchronously or
TA
is asserted synchronous to
TA
deasserted. In typical
TA
input is ignored.
TA
RAS
input
,
2-5