DSPB56364FU100 Freescale Semiconductor, DSPB56364FU100 Datasheet - Page 37

• Manufacturer Part Number: DSPB56364FU100
• Manufacturer: Freescale Semiconductor

Specifications of DSPB56364FU100

• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 9KB
• Program Memory Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.14V
• Operating Supply Voltage (max): 3.46V
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• Lead Free Status / Rohs Status: Not Compliant

1
2
3
4
5
6
7
Freescale Semiconductor
No.
147 Last WR assertion to RAS deassertion
148 WR assertion to CAS deassertion
149 Data valid to CAS assertion (write)
150 CAS assertion to data not valid (write)
151 WR assertion to CAS assertion
152 Last RD assertion to RAS deassertion
153 RD assertion to data valid
154 RD deassertion to data not valid
155 WR assertion to data active
156 WR deassertion to data high impedance
The number of wait states for Page mode access is specified in the DCR.
The refresh period is specified in the DCR.
The asynchronous delays specified in the expressions are valid for DSP56364.
There are no DRAMs fast enough to fit to two wait states Page mode @ 100 MHz (See
All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., t
read-after-read or write-after-write sequences).
BRW[1:0] (DRAM Control Register bits) defines the number of wait states that should be inserted in each DRAM out-of-page
access.
RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t
Table 3-10 DRAM Page Mode Timings, Two Wait States
Characteristics
7
DSP56364 Technical Data, Rev. 4.1
Symbol
t
t
t
t
CWL
WCS
ROH
RWL
t
t
t
t
DS
DH
GA
GZ
2.75 × T
0.25 × T
0.25 × T
1.75 × T
1.75 × T
1.75 × T
0.75 × T
2.5 × T
2.5 × T
Expression
0.25 × T
T
C
− 4.3
C
C
C
C
C
C
C
C
C
− 4.3
− 4.0
− 4.3
− 3.7
− 3.0
− 4.0
− 7.5
− 6.5
− 0.3
C
5
External Memory Expansion Port (Port A)
1, 2, 3, 4
33.4
33.6
22.5
10.9
33.9
11.1
Min
0.1
0.0
—
—
—
—
66 MHz
Figure 3-11
OFF
(continued)
Max
19.0
3.8
—
—
—
—
—
—
—
—
—
—
and not t
26.8
27.0
17.9
27.3
).
Min
0.1
8.2
0.0
9.1
—
—
—
—
PC
80 MHz
GZ.
equals 3 × T
Max
15.4
3.1
—
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
C
3-21
for