TE28F400B3B90 Intel, TE28F400B3B90 Datasheet
TE28F400B3B90
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TE28F400B3B90 Summary of contents
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... Automated Program and Block Erase — Status Registers Notice: This document contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. Preliminary Datasheet ® ...
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... Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right ...
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Contents 1.0 Introduction .................................................................................................................. 1 1.1 Product Overview .................................................................................................. 2 2.0 Product Description 2.1 Package Pinouts ...................................................................................................3 2.2 Block Organization .............................................................................................. 10 2.2.1 Parameter Blocks ................................................................................... 10 2.2.2 Main Blocks ............................................................................................10 3.0 Principles of Operation 3.1 Bus Operation ..................................................................................................... 10 ...
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Reset Operations 6.0 Ordering Information 7.0 Additional Information A Write State Machine Current/Next States B Architecture Block Diagram C Word-Wide Memory Map Diagrams D Byte-Wide Memory Map Diagrams E Program and Erase Flowcharts iv ...
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... BGA package top side mark information added (Section CCS Added Command Sequence Error Note (Table 7) Datasheet renamed from Smart 3 Advanced Boot Block 4-Mbit, 8-Mbit, 16-Mbit Flash -006 Memory Family. Added device ID information for 4-Mbit x8 device Removed 32-Mbit x8 to reflect product offerings Minor text changes ...
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Number -008 4-Mbit packaging and addressing information corrected throughout document -009 Corrected 4-Mbit memory addressing tables in Appendices D and E Max I -010 V CC Added 64-Mbit density and faster speed offerings -011 Removed ...
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... Introduction This datasheet contains the specifications for the 3-Volt Advanced Boot Block Flash Memory family, which is optimized for portable, low-power, systems. This family of products features 1.65 V–2 2.7 V–3.6 V I/Os, and a low V Program, and Erase operations. In addition, this family is capable of fast programming ...
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... Product Overview Intel provides the most flexible voltage solution in the flash industry, providing three discrete voltage supply pins: V Erase operation. All 3-Volt Advanced Boot Block Flash Memory products provide program/erase capability at 2 (for fast production programming), and read with V many designs read from the flash memory a large percentage of the time, 2 ...
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... Product Description This section explains device pin description and package pinouts. 2.1 Package Pinouts The 3-Volt Advanced Boot Block flash memory is available in 40-lead TSOP (x8, 48-lead TSOP (x16, 48-ball VF BGA (x16, upgrades have been circled. Figure 1. 40-Lead TSOP Package for x8 Configurations ...
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Figure 2. 48-Lead TSOP Package for x16 Configurations WE# RP# V ...
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... TSOP products will convert to a white ink triangle as a Pin-1 indicator. Products without the white triangle will continue to use a dimple as a Pin-1 indicator. There are no other changes in package size, materials, functionality, customer handling, or manufacturability. Product will continue to meet stringent Intel quality requirements. Products Affected are Intel Ordering Codes: Preliminary ...
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Ordering Information Valid Combinations Ext. Temp. 32 Mbit Ext. Temp. 16 Mbit Ext. Temp. 8 Mbit 6 40-Lead TSOP 48-Lead TSOP TE28F320B3TC70 TE28F320B3BC70 TE28F320B3TC90 TE28F320B3BC90 TE28F320B3TA100 TE28F320B3BA100 TE28F320B3TA110 TE28F320B3BA110 TE28F160B3TC70 TE28F160B3BC70 TE28F160B3TC80 TE28F160B3BC80 (3) TE28F016B3TA90 ...
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Figure 4. x8 48-Ball µBGA* Chip Size Package (Top View, Ball Down CCQ F GND NOTES: 1. Shaded connections indicate the upgrade address connections. Lower ...
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Figure 5. x16 48-Ball Very Fine Pitch BGA and µBGA* Chip Size Package (Top View, Ball Down CCQ F GND ...
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Table 2. 3-Volt Advanced Boot Block Pin Descriptions Symbol Type ADDRESS INPUTS for memory addresses. Addresses are internally latched during a program or erase cycle. A –A INPUT 28F004B3: A[0-18], 28F008B3: A[0-19], 28F016B3: A[0-20 28F400B3: A[0-17], 28F800B3: A[0-18], ...
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... Advanced Boot Block flash memory devices read, program, and erase in-system via the local CPU or microcontroller. All bus cycles to or from the flash memory conform to standard microcontroller bus cycles. Four control pins dictate the data flow in and out of the flash component: CE#, OE#, WE#, and RP# ...
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... CE# and OE# must be driven active to obtain data at the outputs. CE# is the device selection control; when active, it enables the flash memory device. OE# is the data output control, and it drives the selected memory data onto the I/O bus. For all read modes, WE# and RP# must ...
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... Block-Erase operations CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing status information instead of array data. Intel allow proper CPU initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU ...
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... Issuing this Register command clears those bits to “0.” Puts the device into the intelligent-identifier-read mode, so that reading the device will output 90 Read Identifier the manufacturer and device codes (A address inputs must be 0) ...
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Read Identifier To read the manufacturer and device codes, the device must be in read-identifier mode, which can be reached by writing the Read Identifier command (90H). Once in read-identifier mode, A outputs the ...
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... The only other valid commands while program is suspended are Read Status Register, Read Identifier, and Program Resume. After the Program Resume command is written to the flash memory, the WSM will continue with the program process and status-register bits SR.2 and SR.7 will automatically be cleared. After the Program Resume command is written, the device automatically outputs status-register data when read (see Resume Flowchart) ...
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... Program/Erase Resume NOTES: PA: Program Address IA: Identifier Address 1. Bus operations are defined in 2. Following the Intelligent Identifier command, two Read operations access manufacturer and device codes for manufacturer code Either 40H or 10H command is valid although the standard is 40H. 4. When writing commands to the device, the upper data bus [DQ minimize current draw ...
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... Operation aborted operation to locked blocks SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R) NOTE: A Command Sequence Error is indicated when SR.4, SR.5, and SR.7 are set. 3.3 Block Locking The 3-Volt Advanced Boot Block flash memory architecture features two hardware-lockable parameter blocks. 3.3.1 WP for Block Locking IL The lockable blocks are locked when WP block will result in an error, which will be reflected in the status register ...
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... Power Consumption Intel flash devices have a tiered approach to power savings that can significantly reduce overall system power consumption. The Automatic Power Savings (APS) feature reduces power consumption when the device is selected but idle. If the CE# is deasserted, the flash enters its standby mode, where current consumption is even lower ...
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... Preliminary 28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 current values. Active power is the largest contributor The flash stays in this static state with outputs valid CCS ) and the device in read mode, the flash memory is in standby IH PHQV 4.5). ) powers-up first. (GND 0.2 V). During read modes, IL (see AC Characteristics— ...
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... If a CPU reset occurs without a flash memory reset, proper CPU initialization will not occur because the flash memory may be providing status information instead of array data. Intel recommends connecting RP# to the system CPU RESET# signal to allow proper CPU/flash initialization following system reset. ...
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... Output shorted for no more than one second. No more than one output shorted at a time. NOTICE: This datasheet contains preliminary information on new products in production. Specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before . ...
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Operating Conditions Symbol T Operating Temperature A V CC1 V V CC2 CC V CC3 V CCQ1 V I/O Supply Voltage CCQ2 V CCQ3 V PP1 V PP2 Program and Erase Voltage V PP3 ...
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DC Characteristics Sym Parameter I Input Load Current LI I Output Leakage Current LO V Standby Current for CC 0.13 and 0.18 Micron Product I CCS V Standby Current for CC 0.25 Micron Product V Power-Down Current CC for ...
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DC Characteristics, Continued Sym Parameter Erase Current CC PP for 0.13 and 0.18 Micron Product I CCE +I PPE Erase Current CC PP for 0.25 Micron Product I V ...
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Since each column lists specifications for a different V conditions V Max voltage listed at the top of each column Automatic Power Savings (APS) reduces I 4. Sampled, not 100% tested. 5. Erase and program ...
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AC Characteristics —Read Operations Density Product # Sym Parameter R1 t Read Cycle Time AVAV R2 t Address to Output Delay AVQV ( CE# to Output Delay ELQV ( OE# ...
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AC Characteristics, Continued Density Product 70 ns Para- # Sym meter V 2.7 V–3 Min R1 t Read Cycle Time 70 AVAV Address to Output R2 t AVQV Delay CE# to Output R3 t (1) ELQV Delay OE# ...
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AC Characteristics, Continued Density Product Para- # Sym meter V 2.7 V–3.6 V 2.7 V–3 Min R1 t Read Cycle Time AVAV Address to Output R2 t AVQV Delay CE# to Output R3 ...
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AC Characteristics, Continued # Sym R1 t Read Cycle Time AVAV R2 t Address to Output Delay AVQV R3 t CE# to Output Delay ELQV R4 t OE# to Output Delay GLQV R5 t RP# to Output Delay PHQV R6 ...
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Figure 8. AC Waveform: Read Operations Standby V IH ADDRESSES ( CE# ( OE# ( WE# ( DATA (D/Q) ...
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AC Characteristics —Write Operations # Sym Parameter t / PHWL W1 RP# High Recovery to WE# (CE#) Going Low t PHEL t / ELWL W2 CE# (WE#) Setup to WE# (CE#) Going Low t WLEL t / ELEH W3 ...
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AC Characteristics—Write Operations, continued # Sym Parameter t / RP# High Recovery to WE# (CE#) PHWL W1 t Going Low PHEL t / CE# (WE#) Setup to WE# (CE#) Going ELWL W2 t Low WLEL ...
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AC Characteristics—Write Operations, continued # Sym Parameter t / RP# High Recovery to WE# (CE#) PHWL W1 t Going Low PHEL t / CE# (WE#) Setup to WE# (CE#) Going ELWL W2 t Low WLEL t / ELEH W3 WE# ...
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AC Characteristics—Write Operations, continued # Sym t / PHWL W1 RP# High Recovery to WE# (CE#) Going Low t PHEL t / ELWL W2 CE# (WE#) Setup to WE# (CE#) Going Low t WLEL t ...
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Program and Erase Timings Symbol 8-KB Parameter Block Program Time (Byte) t BWPB 4-KW Parameter Block Program Time (Word) 64-KB Main Block Program Time (Byte) t BWMB 32-KW Main Block Program Time (Word) Byte Program Time Word Program Time ...
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Figure 9. AC Waveform: Program and Erase Operations ADDRESSES [ CE#(WE#) [E(W OE# [ WE#(CE#) [W(E ...
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Reset Operations Figure 10. AC Waveform: Deep Power-Down/Reset Operation Symbol RP# Low to Reset during Read t PLPH (If RP# is tied RP# Low to Reset during Block Erase or Program PLRH NOTES ...
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... Ordering Information Package TE = 48-Lead TSOP GT = 48-Ball µBGA* CSP BGA CSP Product line designator ® for all Intel Flash products Device Density 640 = x16 (64 Mbit) 320 = x16 (32 Mbit) 160 = x16 (16 Mbit) 800 = x16 (8 Mbit) 016 = x8 (16 Mbit) 008 = x8 (8 Mbit) 004 = x8 (4 Mbit) ...
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... TE28F160B3TC80 TE28F160B3BC80 (3) (3) TE28F160B3TA90 (3) (3) TE28F160B3BA90 (3) (3) TE28F160B3TA110 (3) (3) TE28F160B3BA110 (3) TE28F800B3TA90 (3) TE28F800B3BA90 (3) TE28F800B3TA110 (3) TE28F800B3BA110 TE28F400B3T90 TE28F400B3B90 TE28F400B3T110 TE28F400B3B110 (1,2) 48-Ball µBGA CSP 48-Ball VF BGA GE28F640B3TC80 GE28F640B3BC80 GE28F640B3TC100 GE28F640B3BC100 GE28F320B3TD70 GE28F320B3BD70 GE28F320B3TC70 GE28F320B3BC70 GE28F320B3TC90 GE28F320B3BC90 GT28F320B3TA100 GT28F320B3BA100 GT28F320B3TA110 GT28F320B3BA110 GE28F160B3TC70 GE28F160B3BC70 GE28F160B3TC80 ...
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... Intel or distribution sales office. 2. Visit Intel’s World Wide Web home page at http://www.Intel.com or http://developer.intel.com for technical documentation and tools. 3. For the most current information on Intel Advanced and Advanced+ Boot Block Flash memory, visit our microsite at http://developer.intel.com/design/flash/abblock. 40 Document/Tool http://developer ...
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Appendix A Write State Machine Current/Next States Data Read Current State SR.7 When Array Read (FFH) Read Read Array “1” Array Array Read Read Status “1” Status Array Read Read “1” Identifier Identifier Array Prog. Setup “1” Status Program “0” ...
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Appendix B Architecture Block Diagram V CCQ Input Buffer Address Latch Address Counter Output Buffer Identifier Register Status Register Power Data Reduction Comparator Control Y-Decoder Y-Gating/Sensing ...
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Appendix C Word-Wide Memory Map Diagrams 16-Mbit and 32-Mbit Word-Wide Memory Addressing Top Boot Size 16 Mbit (KW) 4 FF000-FFFFF 4 FE000-FEFFF 4 FD000-FDFFF 4 FC000-FCFFF 4 FB000-FBFFF 4 FA000-FAFFF 4 F9000-F9FFF 4 F8000-F8FFF 32 F0000-F7FFF 32 E8000-EFFFF 32 E0000-E7FFF ...
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Word-Wide Memory Addressing (Continued) Top Boot Size 16 Mbit (KW ...
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Word-Wide Memory Addressing Top Boot Size 4 Mbit (KW) 3F000-3FFFF 7F000-7FFFF 3E000-3EFFF 7E000-7EFFF 3D000-3DFFF 7D000-7DFFF 3C000-3CFFF 7C000-7CFFF 3B000-3BFFF 7B000-7BFFF 3A000-3AFFF 7A000-7AFFF 39000-39FFF 79000-79FFF 38000-38FFF 78000-78FFF 4 30000-37FFF 70000-77FFF 4 28000-2FFFF 68000-6FFFF 4 20000-27FFF 60000-67FFF 4 18000-1FFFF 58000-5FFFF ...
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Word-Wide Memory Addressing Top Boot Size 16 Mbit 32 Mbit (KW) 4 FF000-FFFFF 1FF000-1FFFFF 4 FE000-FEFFF 1FE000-1FEFFF 4 FD000-FDFFF 1FD000-1FDFFF 4 FC000-FCFFF 1FC000-1FCFFF 4 FB000-FBFFF 1FB000-1FBFFF 4 FA000-FAFFF 1FA000-1FAFFF 4 F9000-F9FFF ...
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Word-Wide Memory Addressing (Continued) Top Boot Size 16 Mbit 32 Mbit (KW) 32 0A8000-0AFFFF 32 0A0000-0A7FFF 32 098000-09FFFF 32 090000-097FFF 32 088000-08FFFF 32 080000-087FFF 32 078000-07FFFF 32 070000-077FFF 32 068000-06FFFF 32 060000-067FFF 32 058000-05FFFF 32 050000-057FFF ...
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Word-Wide Memory Addressing (Continued) Top Boot Size 16 Mbit 32 Mbit (KW ...
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Appendix D Byte-Wide Memory Map Diagrams 8-Mbit and 16-Mbit Byte-Wide Byte-Wide Memory Addressing Top Boot Size (KB) 8 Mbit 8 FE000-FFFFF 8 FC000-FDFFF 8 FA000-FBFFF 8 F8000-F9FFF 8 F6000-F7FFF 8 F4000-F5FFF 8 F2000-F3FFF 8 F0000-F1FFF 64 E0000-EFFFF 64 D0000-DFFFF 64 ...
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Byte-Wide Memory Addressing (Continued) Top Boot Size (KB) 8 Mbit ...
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Top Boot Size 4 Mbit (KB) 8 7E000-7FFFF 8 7C000-7DFFF 8 7A000-7BFFF 8 78000-79FFF 8 76000-77FFF 8 74000-75FFF 8 72000-73FFF 8 70000-71FFF 64 60000-6FFFF 64 50000-5FFFF 64 40000-4FFFF 64 30000-3FFFF 64 20000-2FFFF 64 10000-1FFFF 64 00000-0FFFF Preliminary 28F004/400B3, 28F008/800B3, 28F016/160B3, ...
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Appendix E Program and Erase Flowcharts Figure 11. Program Flowchart Start Write 40H Program Address/Data Read Status Register SR Yes Full Status Check if Desired Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR.3 ...
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Figure 12. Program Suspend/Resume Flowchart Start Write B0H Write 70H Read Status Register SR SR Write FFH Read Array Data Done Reading Yes Write D0H Program Resumed Preliminary 28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Operation 0 0 ...
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Figure 13. Block Erase Flowchart Start Write 20H Write D0H and Block Address Read Status Register SR Full Status Check if Desired Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data ...
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Figure 14. Erase Suspend/Resume Flowchart Start Write B0H Write 70H Read Status Register SR SR Write FFH Read Array Data Done Reading Yes Write D0H Erase Resumed Preliminary 28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Bus Operation Write ...
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Preliminary ...
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Introduction 1.1 Product Overview.............................................................................................2 2.0 Product Description 2.1 Package Pinouts ..............................................................................................3 2.2 Block Organization.........................................................................................10 2.2.1 2.2.2 3.0 Principles of Operation 3.1 Bus Operation ................................................................................................10 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.2 Modes of Operation .......................................................................................12 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 ...
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Working page only. Do not distribute. B Architecture Block Diagram C Word-Wide Memory Map Diagrams D Byte-Wide Memory Map Diagrams E Program and Erase Flowcharts 58 ........................................................................... 41 ............................................................. 42 .............................................................. 48 .................................................................... 51 ...