IS42S16100A1-7T ISSI, Integrated Silicon Solution Inc, IS42S16100A1-7T Datasheet - Page 28
![no-image](/images/manufacturer_photos/0/3/347/issi__integrated_silicon_solution_inc_sml.jpg)
IS42S16100A1-7T
Manufacturer Part Number
IS42S16100A1-7T
Description
Manufacturer
ISSI, Integrated Silicon Solution Inc
Type
SDRAMr
Datasheet
1.IS42S16100A1-7T.pdf
(79 pages)
Specifications of IS42S16100A1-7T
Organization
1Mx16
Density
16Mb
Address Bus
12b
Access Time (max)
6/5.5ns
Maximum Clock Rate
143MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
130mA
Pin Count
50
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IS42S16100A1-7T
Manufacturer:
ISSI
Quantity:
503
Company:
Part Number:
IS42S16100A1-7TL
Manufacturer:
ISSI
Quantity:
16
28
IS42S16100A1
CAS latency = 3, burstlength = 4
Interval Between Write and Read Commands
A new read command can be executed while a write cycle
is in progress, i.e., before that cycle completes. Data
corresponding to the new read command is output after the
CAS latency has elapsed from the point the new read
command was executed. The I/On pins must be placed in
the HIGH impedance state at least one cycle before data
is output during this operation.
CAS latency = 2, burstlength = 4
COMMAND
COMMAND
CLK
CLK
DQ
DQ
WRITE (CA=A, BANK 0)
WRITE (CA=A, BANK 0)
D
D
WRITE A0
WRITE A0
IN
IN
A0
A0
READ B0
READ B0
t
t
CCD
CCD
READ (CA=B, BANK 0)
READ (CA=B, BANK 0)
HI-Z
Integrated Silicon Solution, Inc. — www.issi.com —
D
OUT
HI-Z
B0
The interval (t
clock cycle.
The selected bank must be set to the active state before
executing this command.
D
D
OUT
OUT
B0
B1
D
D
OUT
OUT
CCD
B2
B1
) between command must be at least one
D
D
OUT
OUT
B3
B2
D
OUT
B3
ISSI
1-800-379-4774
08/12/03
Rev. C
®