CAT93C46S-TE13 ON Semiconductor, CAT93C46S-TE13 Datasheet - Page 7

• Manufacturer Part Number: CAT93C46S-TE13
• Manufacturer: ON Semiconductor

Specifications of CAT93C46S-TE13

• Density: 1Kb
• Interface Type: Serial (Microwire)
• Organization: 128x8/64x16
• Access Time (max): 500ns
• Frequency (max): 1MHz
• Write Protection: Yes
• Data Retention: 100Year
• Operating Supply Voltage (typ): 3.3/5V
• Package Type: SOIC N
• Operating Temp Range: 0C to 70C
• Supply Current: 3mA
• Operating Supply Voltage (min): 2.5V
• Operating Supply Voltage (max): 6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / Rohs Status: Not Compliant

Figure 4. Erase Instruction Timing
Erase
Upon receiving an ERASE command and address, the
CS (Chip Select) pin must be deasserted for a minimum
of t
clear cycle of the selected memory location. The clocking
of the SK pin is not necessary after the device has
entered the self clocking mode. (Note 1.) The ready/
busy status of the CAT93C46/56/57/66/86 can be
determined by selecting the device and polling the DO
pin. Once cleared, the content of a cleared location
returns to a logical “1” state.
Erase/Write Enable and Disable
The CAT93C46/56/57/66/86 powers up in the write
disable state. Any writing after power-up or after an
EWDS (write disable) instruction must first be preceded
by the EWEN (write enable) instruction. Once the write
instruction is enabled, it will remain enabled until power
to the device is removed, or the EWDS instruction is
sent. The EWDS instruction can be used to disable all
CAT93C46/56/57/66/86 write and clear instructions,
and will prevent any accidental writing or clearing of the
device. Data can be read normally from the device
regardless of the write enable/disable status.
DO
CS
SK
CSMIN
DI
. The falling edge of CS will start the self clocking
1
1
1
A N
A N-1
HIGH-Z
7
A 0
Erase All
Upon receiving an ERAL command, the CS (Chip Select)
pin must be deselected for a minimum of t
falling edge of CS will start the self clocking clear cycle
of all memory locations in the device. The clocking of the
SK pin is not necessary after the device has entered the
self clocking mode. (Note 1.) The ready/busy status of
the CAT93C46/56/57/66/86 can be determined by
selecting the device and polling the DO pin. Once
cleared, the contents of all memory bits return to a logical
“1” state.
Write All
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
t
data write to all memory locations in the device. The
clocking of the SK pin is not necessary after the device
has entered the self clocking mode. (Note 1.) The ready/
busy status of the CAT93C46/56/57/66/86 can be
determined by selecting the device and polling the DO
pin. It is not necessary for all memory locations to be
cleared before the WRAL command is executed.
Note 1: This note is applicable only to the CAT93C46.
After the last data bit has been sampled, Chip Select
(CS) must be brought Low before the next rising edge of
the clock (SK) in order to start the self-timed high voltage
cycle. This is important because if the CS is brought low
before or after this specific frame window, the addressed
location will not be programmed or erased.
CSMIN
. The falling edge of CS will start the self clocking
t SV
t EW
STATUS VERIFY
BUSY
t CS
READY
STANDBY
t HZ
93C46/56/57/66/86 F06
Doc. No. 1023, Rev. C
HIGH-Z
CSMIN
. The