CAT93C46S-TE13 ON Semiconductor, CAT93C46S-TE13 Datasheet - Page 6

• Manufacturer Part Number: CAT93C46S-TE13
• Manufacturer: ON Semiconductor

Specifications of CAT93C46S-TE13

• Density: 1Kb
• Interface Type: Serial (Microwire)
• Organization: 128x8/64x16
• Access Time (max): 500ns
• Frequency (max): 1MHz
• Write Protection: Yes
• Data Retention: 100Year
• Operating Supply Voltage (typ): 3.3/5V
• Package Type: SOIC N
• Operating Temp Range: 0C to 70C
• Supply Current: 3mA
• Operating Supply Voltage (min): 2.5V
• Operating Supply Voltage (max): 6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / Rohs Status: Not Compliant

Figure 3. Write Instruction Timing
The format for all instructions sent to the device is a
logical "1" start bit, a 2-bit (or 4-bit) opcode, 6-bit (93C46)/
/7-bit (93C57)/ 8-bit (93C56 or 93C66)/10-bit (93C86)
(an additional bit when organized X8) and for write
operations a 16-bit data field (8-bit for X8 organizations).
Note: This note is applicable only to 93C86. The Write,
Erase, Write all and Erase all instructions require PE=1.
If PE is left floating, 93C86 is in Program Enabled mode.
For Write Enable and Write Disable instruction PE=don’t
care.
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93C46/
56/57/66/86 will come out of the high impedance state
and, after sending an initial dummy zero bit, will begin
shifting out the data addressed (MSB first). The output
data bits will toggle on the rising edge of the SK clock and
are stable after the specified time delay (t
After the initial data word has been shifted out and CS
remains asserted with the SK clock continuing to toggle,
the CAT93C46/56/66/86 will automatically increment to
Figure 2b. Read Instruction Timing (93C56/57/66/86)
93C46/56/57/66/86
Doc. No. 1023, Rev. C
DO
SK
CS
DI
DO
CS
SK
DI
1
1
1
1
0
1
1
0
1
HIGH-Z
A N
A N
1
A N–1
A N-1
1
PD0
1
HIGH-Z
Dummy 0
or t
1
PD1
)
A 0
1
A 0
6
1
D 15 . . . D 0
or
D 7 . . . D 0
D N
the next address and shift out the next data word in a
sequential READ mode. As long as CS is continuously
asserted and SK continues to toggle, the device will
keep incrementing to the next address automatically
until it reaches to the end of the address space, then
loops back to address 0. In the sequential READ mode,
only the initial data word is preceeded by a dummy zero
bit. All subsequent data words will follow without a
dummy zero bit.
Write
After receiving a WRITE command, address and the
data, the CS (Chip Select) pin must be deselected for a
minimum of t
self clocking clear and data store cycle of the memory
location specified in the instruction. The clocking of the
SK pin is not necessary after the device has entered the
self clocking mode. (Note 1.) The ready/busy status of
the CAT93C46/56/57/66/86 can be determined by
selecting the device and polling the DO pin. Since this
device features Auto-Clear before write, it is NOT
necessary to erase a memory location before it is written
into.
1
1
Address + 1
D 15 . . . D 0
or
D 7 . . . D 0
D 0
1
Don't Care
CSMIN
t SV
1
t EW
Address + 2
D 15 . . . D 0
or
D 7 . . . D 0
. The falling edge of CS will start the
t CS
1
STATUS
VERIFY
BUSY
1
READY
Address + n
D 15 . . .
or
D 7 . . .
HIGH-Z
STANDBY
t HZ
93C46/56/57/66/86 F05