M50LPW040K1 Micron Technology Inc, M50LPW040K1 Datasheet - Page 8

• Manufacturer Part Number: M50LPW040K1
• Manufacturer: Micron Technology Inc

Specifications of M50LPW040K1

• Cell Type: NOR
• Density: 4Mb
• Access Time (max): 11/50ns
• Interface Type: Parallel/Serial
• Boot Type: Top
• Address Bus: 4/11Bit
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: PLCC
• Sync/async: Async/Sync
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 512K
• Supply Current: 20mA
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / Rohs Status: Compliant

M50LPW040
Table 6. LPC Bus Read Field Definitions
Figure 5. LPC Bus Read Waveforms
8/36
Number
Clock
Cycle
13-14
16-17
3-10
11
12
15
18
19
1
2
CLK
LFRAME
LAD0-LAD3
Number of
clock cycles
Count
Clock
Cycle
1
1
8
1
1
2
1
2
1
1
CYCTYPE
WSYNC
RSYNC
START
ADDR
+ DIR
Field
DATA
TAR
TAR
TAR
TAR
START
1
LAD0-
CYCTYPE
0000b
0100b
1111b
1111b
0101b
0000b
1111b
1111b
XXXX
XXXX
LAD3
(float)
(float)
+ DIR
1
Memory
ADDR
N/A
I/O
O
O
O
O
O
8
I
I
I
I
On the rising edge of CLK with LFRAME Low, the contents
of LAD0-LAD3 must be 0000b to indicate the start of a LPC
cycle.
Indicates the type of cycle. Bits 3:2 must be 01b. Bit 1
indicates the direction of transfer: 0b for read. Bit 0 is 0
A 32-bit address phase is transferred starting with the most
significant nibble first. A23-A31 must be set to 1. A22 = 1 for
Array, A22 = 0 for registers access. For A19-A21 values,
refer to Table 2.
The host drives LAD0-LAD3 to 1111b to indicate a
turnaround cycle.
The LPC Flash Memory takes control of LAD0-LAD3 during
this cycle.
The LPC Flash Memory drives LAD0-LAD3 to 0101b (short
wait-sync) for two clock cycles, indicating that the data is not
yet available. Two wait-states are always included.
The LPC Flash Memory drives LAD0-LAD3 to 0000b,
indicating that data will be available during the next clock
cycle.
Data transfer is two CLK cycles, starting with the least
significant nibble.
The LPC Flash Memory drives LAD0-LAD3 to 1111b to
indicate a turnaround cycle.
The LPC Flash Memory floats its outputs, the host takes
control of LAD0-LAD3.
TAR
2
SYNC
3
DATA
2
Description
TAR
2
AI04429