M50LPW040K1 Micron Technology Inc, M50LPW040K1 Datasheet - Page 7

• Manufacturer Part Number: M50LPW040K1
• Manufacturer: Micron Technology Inc

Specifications of M50LPW040K1

• Cell Type: NOR
• Density: 4Mb
• Access Time (max): 11/50ns
• Interface Type: Parallel/Serial
• Boot Type: Top
• Address Bus: 4/11Bit
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: PLCC
• Sync/async: Async/Sync
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 512K
• Supply Current: 20mA
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / Rohs Status: Compliant

Table 5. Block Addresses
Note: For A19 value, refer to Table 2.
Bus Read. Bus Read operations read from the
memory cells, specific registers in the Command
Interface or Low Pin Count Registers. A valid Bus
Read operation starts when Input Communication
Frame, LFRAME, is Low, V
the correct Start cycle is on LAD0-LAD3. On the
following clock cycles the Host will send the Cycle
Type + Dir, Address and other control bits on
LAD0-LAD3. The memory responds by outputting
Sync data until the wait-states have elapsed
followed by Data0-Data3 and Data4-Data7.
Refer to Table 6, and Figure 5, for a description of
the Field definitions for each clock cycle of the
transfer. See Table 22, LPC Interface AC Signal
Timing Characteristics and Figure 10, LPC Inter-
face AC Signal Timing Waveforms, for details on
the timings of the signals.
Bus Write. Bus Write operations write to the
Command Interface or Low Pin Count Registers. A
valid Bus Write operation starts when Input
Communication Frame, LFRAME, is Low, V
Clock rises and the correct Start cycle is on LAD0-
LAD3. On the following Clock cycles the Host will
send the Cycle Type + Dir, Address, other control
bits, Data0-Data3 and Data4-Data7 on LAD0-
LAD3. The memory outputs Sync data until the
wait-states have elapsed.
(Kbytes)
Size
64
64
64
64
64
64
64
64
Address Range
70000h-7FFFFh
60000h-6FFFFh
50000h-5FFFFh
40000h-4FFFFh
30000h-3FFFFh
20000h-2FFFFh
10000h-1FFFFh
00000h-0FFFFh
Number
IL
Block
, as Clock rises and
7
6
5
4
3
2
1
0
Block Type
Main Block
Main Block
Main Block
Main Block
Main Block
Main Block
Main Block
Top Block
IL
, as
Refer to Table 7, LPC Bus Write Field Definitions,
and Figure 6, LPC Bus Write Waveforms, for a
description of the Field definitions for each clock
cycle of the transfer. See Table 22, LPC Interface
AC Signal Timing Characteristics and Figure 10,
LPC Interface AC Signal Timing Waveforms, for
details on the timings of the signals.
Bus Abort. The Bus Abort operation can be used
to immediately abort the current bus operation. A
Bus Abort occurs when LFRAME is driven Low,
V
state the Input/Output Communication pins,
LAD0-LAD3.
Note that, during a Bus Write operation, the
Command
command as soon as the data is fully received; a
Bus Abort during the final TAR cycles is not
guaranteed to abort the command; the bus,
however, will be released immediately.
Standby. When LFRAME is High, V
memory is put into Standby mode where LAD0-
LAD3 are put into a high-impedance state and the
Supply Current is reduced to the Standby level,
I
Reset. During Reset mode all internal circuits are
switched off, the memory is deselected and the
outputs are put in high-impedance. The memory is
in Reset mode when Interface Reset, RP, or CPU
Reset, INIT, is Low, V
Low, V
mode upon return from Reset mode and the Lock
Registers return to their default states regardless
of their state before Reset, see Table 15. If RP or
INIT goes Low, V
operation, the operation is aborted and the
memory cells affected no longer contain valid
data; the memory can take up to t
Program or Erase operation.
Block Protection. Block
forced using the signals Top Block Lock, TBL, and
Write Protect, WP, regardless of the state of the
Lock Registers.
CC1
IL
, during the bus operation; the memory will tri-
.
IL
, for t
Interface
PLPH
IL
. The memory resets to Read
, during a Program or Erase
IL
. RP or INIT must be held
starts
Protection
executing
PLRH
M50LPW040
to abort a
can
IH
, the
7/36
the
be