GE28F320J3A110 Intel, GE28F320J3A110 Datasheet - Page 38

• Manufacturer Part Number: GE28F320J3A110
• Manufacturer: Intel

Specifications of GE28F320J3A110

• Cell Type: NOR
• Density: 32Mb
• Access Time (max): 110ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 22/21Bit
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: VFBGA
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 4M/2M
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

28F256J3, 28F128J3, 28F640J3, 28F320J3
10.1.2
38
ECR[15:14]
ECR[13]
ECR[12:0]
Set Enhanced
Configuration Register
(Set ECR)
Res.
ECR
.15
R
Table 15. Enhanced Configuration Register
Table 16. J3C Asynchronous 8-Word Page Mode Command Bus-Cycle Definition
BITS
Command
Note: For forward compatibility reasons, if the 8-word Asynchronous Page mode is to be used on J3C, a
ECR
.14
R
Reserved
Reserved
ECR
To perform a page mode read after any other operation, the Read Array command must be issued to
read from the flash array. Asynchronous page mode reads are permitted in all blocks and are used
to access register information. During register access, only one word is loaded into the page buffer.
Enhanced Configuration Register (ECR)
The Enhanced Configuration Register (ECR) is a volatile storage register that when addressed to
by the Set Enhanced Configuration Register command, and can select between Four-Word Page
mode and Eight-Word Page mode. The ECR is volatile; all bits will be reset to default values when
RP# is deasserted or power is removed from the device. To modify ECR settings, use the Set
Enhanced Configuration Register command. The Set Enhanced Configuration Register command
is written along with the configuration register value, which is placed on the lower 16 bits of the
address bus A[15:0]. This is followed by a second write that confirms the operation and again
presents the enhanced configuration register data on the address bus. After executing this
command, the device returns to Read Array mode. The ECR is shown in
Configuration Register” on page
Clear Status Register command must be issued after issuing the Set Enhanced Configuration
Register command. See
Definition” on page 38
8W
NOTE: Any reserved bits should be set to 0.
NOTE: X = Any valid address within the device. ECD = Enhanced Configuration Register Data.
.13
• “1” = 8Word Page mode
• “0” = 4Word Page mode
ECR
.12
R
Cycles
Req’d.
Bus
3
ECR
.11
R
DESCRIPTION
Oper
Write
ECR
.10
R
for further details.
Table 16, “J3C Asynchronous 8-Word Page Mode Command Bus-Cycle
First Bus Cycle
ECR
Addr
.9
R
ECD
38.
(1)
ECR
R
.8
Data
0x60
ECR
Reserved
.7
R
Oper
Write
ECR
.6
R
Second Bus Cycle
Reserved for Future Use. Set to 0 until further
notice.
Reserved for Future Use. Set to 0 until further
notice.
ECR
Addr
.5
ECD
R
(1)
ECR
.4
R
Data
0x04
ECR
.3
R
NOTES
Table 15, “Enhanced
Oper
Write
ECR
Third Bus Cycle
.2
R
Addr
X
ECR
R
.1
(1)
Datasheet
Data
0x50
ECR
R
.0