CY7C1514V18-250BZXC Cypress Semiconductor Corp, CY7C1514V18-250BZXC Datasheet - Page 19

• Manufacturer Part Number: CY7C1514V18-250BZXC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1514V18-250BZXC

• Density: 72Mb
• Access Time (max): 0.45ns
• Sync/async: Synchronous
• Architecture: QDR
• Clock Freq (max): 250MHz
• Operating Supply Voltage (typ): 1.8V
• Address Bus: 21b
• Package Type: FBGA
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 950mA
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 1.9V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 165
• Word Size: 36b
• Number Of Words: 2M
• Lead Free Status / Rohs Status: Compliant

Power Up Sequence in QDR-II SRAM
QDR-II SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations.
Power Up Sequence
■
■
Document #: 38-05489 Rev. *F
Apply power and drive DOFF either HIGH or LOW (All other
inputs can be HIGH or LOW).
❐
❐
❐
Provide stable DOFF (HIGH), power and clock (K, K) for 1024
cycles to lock the DLL.
Apply V
Apply V
Drive DOFF HIGH.
V
DD
/
DOFF
V
DD
DDQ
DDQ
before V
K
K
before V
DDQ
REF
.
or at the same time as V
Unstable Clock
Clock Start (Clock Starts after
V
DD
Figure 3. Power Up Waveforms
/
V
REF
DDQ
.
V
Stable (< +/- 0.1V DC per 50ns )
DD
/
V
DLL Constraints
■
■
■
DDQ
DLL uses K clock as its synchronizing input. The input must
have low phase jitter, which is specified as t
The DLL functions at frequencies down to 120 MHz.
If the input clock is unstable and the DLL is enabled, then the
DLL may lock onto an incorrect frequency, causing unstable
SRAM behavior. To avoid this, provide1024 cycles stable clock
to relock to the desired clock frequency.
Fix High (or tie to V DDQ )
> 1024 Stable clock
Stable)
CY7C1510V18, CY7C1525V18
CY7C1512V18, CY7C1514V18
Start Normal
Operation
KC Var
Page 19 of 29
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